xilinx.com customized_ip blk_mem_gen_0 1.0 CLK.ACLK ACLK AXI4 Interconnect Clock Input CLK s_aclk ASSOCIATED_BUSIF AXI_SLAVE_S_AXI:AXILite_SLAVE_S_AXI ASSOCIATED_RESET s_aresetn FREQ_HZ 100000000 none PHASE 0.000 none CLK_DOMAIN none INSERT_VIP 0 simulation.rtl RST.ARESETN ARESETN AXI4 Interconnect Reset Input RST s_aresetn POLARITY ACTIVE_LOW INSERT_VIP 0 simulation.rtl AXI_SLAVE_S_AXI AXI_SLAVE AXI_SLAVE ARADDR s_axi_araddr ARBURST s_axi_arburst ARID s_axi_arid ARLEN s_axi_arlen ARREADY s_axi_arready ARSIZE s_axi_arsize ARVALID s_axi_arvalid AWADDR s_axi_awaddr AWBURST s_axi_awburst AWID s_axi_awid AWLEN s_axi_awlen AWREADY s_axi_awready AWSIZE s_axi_awsize AWVALID s_axi_awvalid BID s_axi_bid BREADY s_axi_bready BRESP s_axi_bresp BVALID s_axi_bvalid RDATA s_axi_rdata RID s_axi_rid RLAST s_axi_rlast RREADY s_axi_rready RRESP s_axi_rresp RVALID s_axi_rvalid WDATA s_axi_wdata WLAST s_axi_wlast WREADY s_axi_wready WSTRB s_axi_wstrb WVALID s_axi_wvalid DATA_WIDTH 1 none PROTOCOL AXI4LITE none FREQ_HZ 100000000 none ID_WIDTH 0 none ADDR_WIDTH 1 none AWUSER_WIDTH 0 none ARUSER_WIDTH 0 none WUSER_WIDTH 0 none RUSER_WIDTH 0 none BUSER_WIDTH 0 none READ_WRITE_MODE READ_WRITE none HAS_BURST 0 none HAS_LOCK 0 none HAS_PROT 0 none HAS_CACHE 0 none HAS_QOS 0 none HAS_REGION 0 none HAS_WSTRB 0 none HAS_BRESP 0 none HAS_RRESP 0 none SUPPORTS_NARROW_BURST 0 none NUM_READ_OUTSTANDING 1 none NUM_WRITE_OUTSTANDING 1 none MAX_BURST_LENGTH 1 none PHASE 0.000 none CLK_DOMAIN none NUM_READ_THREADS 1 none NUM_WRITE_THREADS 1 none RUSER_BITS_PER_BYTE 0 none WUSER_BITS_PER_BYTE 0 none INSERT_VIP 0 simulation.rtl false AXILite_SLAVE_S_AXI AXILite_SLAVE AXILite_SLAVE ARADDR s_axi_araddr ARBURST s_axi_arburst ARID s_axi_arid ARLEN s_axi_arlen ARREADY s_axi_arready ARSIZE s_axi_arsize ARVALID s_axi_arvalid AWADDR s_axi_awaddr AWBURST s_axi_awburst AWID s_axi_awid AWLEN s_axi_awlen AWREADY s_axi_awready AWSIZE s_axi_awsize AWVALID s_axi_awvalid BID s_axi_bid BREADY s_axi_bready BRESP s_axi_bresp BVALID s_axi_bvalid RDATA s_axi_rdata RID s_axi_rid RLAST s_axi_rlast RREADY s_axi_rready RRESP s_axi_rresp RVALID s_axi_rvalid WDATA s_axi_wdata WLAST s_axi_wlast WREADY s_axi_wready WSTRB s_axi_wstrb WVALID s_axi_wvalid DATA_WIDTH 1 none PROTOCOL AXI4LITE none FREQ_HZ 100000000 none ID_WIDTH 0 none ADDR_WIDTH 1 none AWUSER_WIDTH 0 none ARUSER_WIDTH 0 none WUSER_WIDTH 0 none RUSER_WIDTH 0 none BUSER_WIDTH 0 none READ_WRITE_MODE READ_WRITE none HAS_BURST 0 none HAS_LOCK 0 none HAS_PROT 0 none HAS_CACHE 0 none HAS_QOS 0 none HAS_REGION 0 none HAS_WSTRB 0 none HAS_BRESP 0 none HAS_RRESP 0 none SUPPORTS_NARROW_BURST 0 none NUM_READ_OUTSTANDING 1 none NUM_WRITE_OUTSTANDING 1 none MAX_BURST_LENGTH 1 none PHASE 0.000 none CLK_DOMAIN none NUM_READ_THREADS 1 none NUM_WRITE_THREADS 1 none RUSER_BITS_PER_BYTE 0 none WUSER_BITS_PER_BYTE 0 none INSERT_VIP 0 simulation.rtl false BRAM_PORTA BRAM_PORTA BRAM_PORTA ADDR addra CLK clka DIN dina DOUT douta EN ena RST rsta WE wea MEM_SIZE 8192 none MEM_WIDTH 32 none MEM_ECC NONE none MASTER_TYPE OTHER none READ_WRITE_MODE none READ_LATENCY 1 none true BRAM_PORTB BRAM_PORTB BRAM_PORTB ADDR addrb CLK clkb DIN dinb DOUT doutb EN enb RST rstb WE web MEM_SIZE 8192 none MEM_WIDTH 32 none MEM_ECC NONE none MASTER_TYPE OTHER none READ_WRITE_MODE none READ_LATENCY 1 none false S_1 Mem0 0 4096 32 memory read-write OFFSET_BASE_PARAM C_BASEADDR OFFSET_HIGH_PARAM C_HIGHADDR xilinx_veriloginstantiationtemplate Verilog Instantiation Template verilogSource:vivado.xilinx.com:synthesis.template verilog xilinx_veriloginstantiationtemplate_view_fileset GENtimestamp Fri Sep 30 16:57:39 UTC 2022 outputProductCRC 9:c7757400 xilinx_vhdlsynthesis VHDL Synthesis vhdlSource:vivado.xilinx.com:synthesis vhdl blk_mem_gen_v8_4_2 xilinx_vhdlsynthesis_view_fileset GENtimestamp Fri Sep 30 16:57:39 UTC 2022 outputProductCRC 9:c7757400 xilinx_vhdlsynthesiswrapper VHDL Synthesis Wrapper vhdlSource:vivado.xilinx.com:synthesis.wrapper vhdl blk_mem_gen_0 xilinx_vhdlsynthesiswrapper_view_fileset GENtimestamp Fri Sep 30 16:57:39 UTC 2022 outputProductCRC 9:c7757400 xilinx_anylanguagebehavioralsimulation Simulation :vivado.xilinx.com:simulation blk_mem_gen_v8_4_2 xilinx_anylanguagebehavioralsimulation_view_fileset GENtimestamp Fri Sep 30 16:57:39 UTC 2022 outputProductCRC 9:b409ea18 xilinx_verilogsimulationwrapper Verilog Simulation Wrapper verilogSource:vivado.xilinx.com:simulation.wrapper verilog blk_mem_gen_0 xilinx_verilogsimulationwrapper_view_fileset GENtimestamp Fri Sep 30 16:57:39 UTC 2022 outputProductCRC 9:b409ea18 xilinx_project_archive Miscellaneous :vivado.xilinx.com:misc.files xilinx_project_archive_view_fileset GENtimestamp Fri Sep 30 16:57:39 UTC 2022 outputProductCRC 9:c7757400 xilinx_versioninformation Version Information :vivado.xilinx.com:docs.versioninfo xilinx_versioninformation_view_fileset GENtimestamp Fri Sep 30 16:57:39 UTC 2022 outputProductCRC 9:c7757400 xilinx_externalfiles External Files :vivado.xilinx.com:external.files xilinx_externalfiles_view_fileset GENtimestamp Fri Sep 30 16:58:45 UTC 2022 outputProductCRC 9:c7757400 clka in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 true rsta in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false ena in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false regcea in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false wea in 0 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 true addra in 5 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 true dina in 7 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 true douta out 7 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation true clkb in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false rstb in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false enb in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false regceb in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false web in 0 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false addrb in 5 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false dinb in 7 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false doutb out 7 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false injectsbiterr in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false injectdbiterr in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false eccpipece in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false sbiterr out std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false dbiterr out std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false rdaddrecc out 5 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false sleep in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false deepsleep in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false shutdown in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false rsta_busy out std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false rstb_busy out std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_aclk in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0x0 false s_aresetn in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_awid in 3 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_awaddr in 31 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_awlen in 7 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_awsize in 2 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_awburst in 1 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_awvalid in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_awready out std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_wdata in 7 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_wstrb in 0 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_wlast in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_wvalid in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_wready out std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_bid out 3 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_bresp out 1 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_bvalid out std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_bready in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_arid in 3 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_araddr in 31 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_arlen in 7 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_arsize in 2 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_arburst in 1 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_arvalid in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_arready out std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_rid out 3 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_rdata out 7 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_rresp out 1 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_rlast out std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_rvalid out std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_rready in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_injectsbiterr in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_injectdbiterr in std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation 0 false s_axi_sbiterr out std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_dbiterr out std_logic xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false s_axi_rdaddrecc out 5 0 std_logic_vector xilinx_vhdlsynthesis xilinx_anylanguagebehavioralsimulation false C_FAMILY artix7 C_XDEVICEFAMILY artix7 C_ELABORATION_DIR ./ C_INTERFACE_TYPE 0 C_AXI_TYPE 1 C_AXI_SLAVE_TYPE 0 C_USE_BRAM_BLOCK 0 C_ENABLE_32BIT_ADDRESS 0 C_CTRL_ECC_ALGO NONE C_HAS_AXI_ID 0 C_AXI_ID_WIDTH 4 C_MEM_TYPE 0 C_BYTE_SIZE 9 C_ALGORITHM 1 C_PRIM_TYPE 1 C_LOAD_INIT_FILE 1 C_INIT_FILE_NAME blk_mem_gen_0.mif C_INIT_FILE blk_mem_gen_0.mem C_USE_DEFAULT_DATA 1 C_DEFAULT_DATA 0 C_HAS_RSTA 0 C_RST_PRIORITY_A CE C_RSTRAM_A 0 C_INITA_VAL 0 C_HAS_ENA 0 C_HAS_REGCEA 0 C_USE_BYTE_WEA 0 C_WEA_WIDTH 1 C_WRITE_MODE_A NO_CHANGE C_WRITE_WIDTH_A 8 C_READ_WIDTH_A 8 C_WRITE_DEPTH_A 64 C_READ_DEPTH_A 64 C_ADDRA_WIDTH 6 C_HAS_RSTB 0 C_RST_PRIORITY_B CE C_RSTRAM_B 0 C_INITB_VAL 0 C_HAS_ENB 0 C_HAS_REGCEB 0 C_USE_BYTE_WEB 0 C_WEB_WIDTH 1 C_WRITE_MODE_B WRITE_FIRST C_WRITE_WIDTH_B 8 C_READ_WIDTH_B 8 C_WRITE_DEPTH_B 64 C_READ_DEPTH_B 64 C_ADDRB_WIDTH 6 C_HAS_MEM_OUTPUT_REGS_A 0 C_HAS_MEM_OUTPUT_REGS_B 0 C_HAS_MUX_OUTPUT_REGS_A 0 C_HAS_MUX_OUTPUT_REGS_B 0 C_MUX_PIPELINE_STAGES 0 C_HAS_SOFTECC_INPUT_REGS_A 0 C_HAS_SOFTECC_OUTPUT_REGS_B 0 C_USE_SOFTECC 0 C_USE_ECC 0 C_EN_ECC_PIPE 0 C_READ_LATENCY_A 1 C_READ_LATENCY_B 1 C_HAS_INJECTERR 0 C_SIM_COLLISION_CHECK ALL C_COMMON_CLK 0 C_DISABLE_WARN_BHV_COLL 0 C_EN_SLEEP_PIN 0 C_USE_URAM 0 C_EN_RDADDRA_CHG 0 C_EN_RDADDRB_CHG 0 C_EN_DEEPSLEEP_PIN 0 C_EN_SHUTDOWN_PIN 0 C_EN_SAFETY_CKT 0 C_DISABLE_WARN_BHV_RANGE 0 C_COUNT_36K_BRAM 0 C_COUNT_18K_BRAM 1 C_EST_POWER_SUMMARY Estimated Power for IP : 2.3883 mW choice_list_5453281d Native AXI4 choice_list_5f2d7eda 16kx1 8kx2 4kx4 2kx9 1kx18 512x36 256x72 choice_list_6e3ded9c 0 1 2 3 choice_list_85010fde 1 2 4 8 16 32 64 128 256 choice_list_89a27b2f 8 9 choice_list_bdf7387e BRAM URAM AUTO choice_list_c8df20f0 NONE ECCH32-7 ECCH64-8 ECCHSIAO32-7 ECCHSIAO64-8 ECCHSIAO128-9 choice_pairs_07c32259 WRITE_FIRST READ_FIRST NO_CHANGE choice_pairs_27c66b0d Stand_Alone BRAM_Controller choice_pairs_2adcaf32 SYNC ASYNC choice_pairs_2d73cdeb Always_Enabled Use_ENB_Pin choice_pairs_3949ecbf Always_Enabled Use_ENA_Pin choice_pairs_3e9ce7ae Minimum_Area Low_Power Fixed_Primitives choice_pairs_44b9b2d1 ALL NONE WARNING_ONLY GENERATE_X_ONLY choice_pairs_63de7f78 CE SR choice_pairs_716d2fba Single_Bit_Error_Injection Double_Bit_Error_Injection Single_and_Double_Bit_Error_Injection choice_pairs_b91edaa2 Memory_Slave Peripheral_Slave choice_pairs_c1013cbe No_ECC Soft_ECC BuiltIn_ECC choice_pairs_e4c322cb AXI4_Full AXI4_Lite choice_pairs_e932d933 Single_Port_RAM Simple_Dual_Port_RAM True_Dual_Port_RAM Single_Port_ROM Dual_Port_ROM xilinx_veriloginstantiationtemplate_view_fileset blk_mem_gen_0.vho vhdlTemplate blk_mem_gen_0.veo verilogTemplate xilinx_vhdlsynthesis_view_fileset blk_mem_gen_0_ooc.xdc xdc USED_IN_implementation USED_IN_out_of_context USED_IN_synthesis blk_mem_gen_0.mif mif hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd vhdlSource blk_mem_gen_v8_4_2 xilinx_vhdlsynthesiswrapper_view_fileset synth/blk_mem_gen_0.vhd vhdlSource xil_defaultlib xilinx_anylanguagebehavioralsimulation_view_fileset blk_mem_gen_0.mif mif simulation/blk_mem_gen_v8_4.v verilogSource USED_IN_ipstatic blk_mem_gen_v8_4_2 blk_mem_gen_v8_4_2 xilinx_verilogsimulationwrapper_view_fileset sim/blk_mem_gen_0.v verilogSource xil_defaultlib xilinx_project_archive_view_fileset summary.log log misc/blk_mem_gen_v8_4.vhd vhdlSource xilinx_versioninformation_view_fileset doc/blk_mem_gen_v8_4_changelog.txt text xilinx_externalfiles_view_fileset blk_mem_gen_0.dcp dcp USED_IN_implementation USED_IN_synthesis xil_defaultlib blk_mem_gen_0_stub.v verilogSource USED_IN_synth_blackbox_stub xil_defaultlib blk_mem_gen_0_stub.vhdl vhdlSource USED_IN_synth_blackbox_stub xil_defaultlib blk_mem_gen_0_sim_netlist.v verilogSource USED_IN_simulation USED_IN_single_language xil_defaultlib blk_mem_gen_0_sim_netlist.vhdl vhdlSource USED_IN_simulation USED_IN_single_language xil_defaultlib The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port Block Memory and Single Port Block Memory LogiCOREs, but is not a direct drop-in replacement. It should be used in all new Xilinx designs. The core supports RAM and ROM functions over a wide range of widths and depths. Use this core to generate block memories with symmetric or asymmetric read and write port widths, as well as cores which can perform simultaneous write operations to separate locations, and simultaneous read operations from the same location. For more information on differences in interface and feature support between this core and the Dual Port Block Memory and Single Port Block Memory LogiCOREs, please consult the data sheet. Component_Name blk_mem_gen_0 true Interface_Type Native true AXI_Type AXI4_Full true AXI_Slave_Type Memory_Slave true Use_AXI_ID false false AXI_ID_Width 4 false Memory_Type Single_Port_RAM true PRIM_type_to_Implement BRAM false Enable_32bit_Address false true ecctype No_ECC false ECC false false softecc false false EN_SLEEP_PIN false true EN_DEEPSLEEP_PIN false false EN_SHUTDOWN_PIN false false EN_ECC_PIPE false false RD_ADDR_CHNG_A false false RD_ADDR_CHNG_B false false Use_Error_Injection_Pins false false Error_Injection_Type Single_Bit_Error_Injection false Use_Byte_Write_Enable false true Byte_Size 9 false Algorithm Minimum_Area true Primitive 8kx2 false Assume_Synchronous_Clk false false Write_Width_A 8 true Write_Depth_A 64 true Read_Width_A 8 true Operating_Mode_A NO_CHANGE true Enable_A Always_Enabled true Write_Width_B 8 false Read_Width_B 8 false Operating_Mode_B WRITE_FIRST false Enable_B Always_Enabled false Register_PortA_Output_of_Memory_Primitives false true Register_PortA_Output_of_Memory_Core false true Use_REGCEA_Pin false false Register_PortB_Output_of_Memory_Primitives false false Register_PortB_Output_of_Memory_Core false false Use_REGCEB_Pin false false register_porta_input_of_softecc false false register_portb_output_of_softecc false false Pipeline_Stages 0 false Load_Init_File true true Coe_File c:/Users/Jafari Chen/Desktop/model_cpu_back/cpu02/cpu.srcs/sources_1/ip/blk_mem_gen_0/data.coe true Fill_Remaining_Memory_Locations true true Remaining_Memory_Locations 0 true Use_RSTA_Pin false true Reset_Memory_Latch_A false false Reset_Priority_A CE false Output_Reset_Value_A 0 false Use_RSTB_Pin false false Reset_Memory_Latch_B false false Reset_Priority_B CE false Output_Reset_Value_B 0 false Reset_Type SYNC false Additional_Inputs_for_Power_Estimation false true Port_A_Clock 100 true Port_A_Write_Rate 50 true Port_B_Clock 0 true Port_B_Write_Rate 0 true Port_A_Enable_Rate 100 true Port_B_Enable_Rate 0 true Collision_Warnings ALL true Disable_Collision_Warnings false true Disable_Out_of_Range_Warnings false true use_bram_block Stand_Alone true MEM_FILE no_mem_loaded true CTRL_ECC_ALGO NONE true EN_SAFETY_CKT false false READ_LATENCY_A 1 true READ_LATENCY_B 1 true Block Memory Generator XPM_MEMORY 2 2018.3