32 lines
557 B
Verilog
32 lines
557 B
Verilog
`timescale 1ns / 1ps
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module MAR_tb;
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reg clk, IMAR, IMARB;
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reg[5:0] Din;//PC计数器传来的地址
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reg [7:0] DinD;//PC计数器传来的地址
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reg rst;
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wire [5:0] Dout;
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MAR u0(clk, IMAR, IMARB,
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Din,DinD, rst, Dout);
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initial begin
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clk = 1'b1;
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rst=0;
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end
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always #5 clk=~clk;
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initial begin
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#10 rst=1;
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#10 Din=6'd12; DinD=8'd33; IMAR=1;IMARB=0;
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#10 Din=6'd13; DinD=8'd34; IMAR=0;
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#10 Din=6'd14; DinD=8'd35; IMAR=1;
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#10 Din=6'd15; DinD=8'd36; IMARB=1;IMAR=0;
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#10 Din=6'd16; DinD=8'd37; IMARB=0;
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#10 Din=6'd17; DinD=8'd38; IMARB=1;
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#10 $stop;
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end
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endmodule
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