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CalebChen 2022-10-07 17:17:24 +08:00
parent 34e8c50e24
commit 251e19c13c
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ip/blk_mem_gen_0/blk_mem_gen_0.dcp Normal file
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11100000
00101000
11011001
00101000
11101001
00100001
11100011
00000010
01100011
11011101
00101001
11011000
00101001
11100010
00010100
11100011
00000100
00100011
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00000001
01000011
10100001
11110110
00011101
00001111
00000000
00000000
00000000
00000000
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00000000
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00011001
00000000
00000000
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00000000
00000000
00000000
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00000000
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00000000

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ip/blk_mem_gen_0/blk_mem_gen_0.veo Normal file
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// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
// IP Revision: 2
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
blk_mem_gen_0 your_instance_name (
.clka(clka), // input wire clka
.wea(wea), // input wire [0 : 0] wea
.addra(addra), // input wire [5 : 0] addra
.dina(dina), // input wire [7 : 0] dina
.douta(douta) // output wire [7 : 0] douta
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file blk_mem_gen_0.v when simulating
// the core, blk_mem_gen_0. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

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ip/blk_mem_gen_0/blk_mem_gen_0.vho Normal file
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-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
-- IP Revision: 2
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT blk_mem_gen_0
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : blk_mem_gen_0
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file blk_mem_gen_0.vhd when simulating
-- the core, blk_mem_gen_0. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.

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ip/blk_mem_gen_0/blk_mem_gen_0.xci Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>xci</spirit:library>
<spirit:name>unknown</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:componentInstances>
<spirit:componentInstance>
<spirit:instanceName>blk_mem_gen_0</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
<spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.MAX_BURST_LENGTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_READ_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_OUTSTANDING">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.NUM_WRITE_THREADS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_ECC">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_SIZE">8192</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MEM_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_LATENCY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.READ_WRITE_MODE"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MASTER_TYPE">OTHER</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_ECC">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_SIZE">8192</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.MEM_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_LATENCY">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTB.READ_WRITE_MODE"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.FREQ_HZ">100000000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">./</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_32BIT_ADDRESS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_DEEPSLEEP_PIN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_ECC_PIPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRA_CHG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_RDADDRB_CHG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 2.3883 mW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">blk_mem_gen_0.mem</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">blk_mem_gen_0.mif</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">NO_CHANGE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_Width">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">c:/Users/Jafari Chen/Desktop/model_cpu_back/cpu02/cpu.srcs/sources_1/ip/blk_mem_gen_0/data.coe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">blk_mem_gen_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Always_Enabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">NO_CHANGE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_A">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csg324</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2018.3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

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################################################################################
#
# (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ]
set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ]
################################################################################

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// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
// Date : Sat Oct 1 00:58:45 2022
// Host : Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim {C:/Users/Jafari
// Chen/Desktop/8bits-model-cpu/cpu_bitstream/cpu.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_sim_netlist.v}
// Design : blk_mem_gen_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "blk_mem_gen_0,blk_mem_gen_v8_4_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_2,Vivado 2018.3" *)
(* NotValidForBitStream *)
module blk_mem_gen_0
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [5:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [7:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [7:0]douta;
wire [5:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [7:0]NLW_U0_doutb_UNCONNECTED;
wire [5:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [5:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [7:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "6" *)
(* C_ADDRB_WIDTH = "6" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.3883 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "blk_mem_gen_0.mem" *)
(* C_INIT_FILE_NAME = "blk_mem_gen_0.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "64" *)
(* C_READ_DEPTH_B = "64" *)
(* C_READ_LATENCY_A = "1" *)
(* C_READ_LATENCY_B = "1" *)
(* C_READ_WIDTH_A = "8" *)
(* C_READ_WIDTH_B = "8" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "64" *)
(* C_WRITE_DEPTH_B = "64" *)
(* C_WRITE_MODE_A = "NO_CHANGE" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "8" *)
(* C_WRITE_WIDTH_B = "8" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
blk_mem_gen_0_blk_mem_gen_v8_4_2 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[7:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[5:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[5:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[7:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module blk_mem_gen_0_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [5:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [5:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
blk_mem_gen_0_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module blk_mem_gen_0_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [5:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [5:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
blk_mem_gen_0_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module blk_mem_gen_0_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [5:0]addra;
input [7:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_13 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_21 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_29 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_5 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ;
wire [5:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000203020003000200010302020100020200030102010002020003020000),
.INIT_01(256'h0302000300010100030200020002020103010200000202010301030101020003),
.INIT_02(256'h0001030103030102020200010100000300000001030200030002000300000100),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000303),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000010201),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("NO_CHANGE"),
.WRITE_MODE_B("NO_CHANGE"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram
(.ADDRARDADDR({1'b0,1'b0,1'b0,addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,1'b0,addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[3:2],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[1:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[7:6],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,dina[5:4]}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_5 ,douta[3:2],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_13 ,douta[1:0]}),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_21 ,douta[7:6],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_29 ,douta[5:4]}),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 }),
.ENARDEN(1'b1),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,wea,wea}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module blk_mem_gen_0_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [5:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [5:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
blk_mem_gen_0_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "6" *) (* C_ADDRB_WIDTH = "6" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.3883 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "blk_mem_gen_0.mem" *)
(* C_INIT_FILE_NAME = "blk_mem_gen_0.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "64" *) (* C_READ_DEPTH_B = "64" *) (* C_READ_LATENCY_A = "1" *)
(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "8" *) (* C_READ_WIDTH_B = "8" *)
(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "1" *)
(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "64" *)
(* C_WRITE_DEPTH_B = "64" *) (* C_WRITE_MODE_A = "NO_CHANGE" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "8" *) (* C_WRITE_WIDTH_B = "8" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_2" *) (* downgradeipidentifiedwarnings = "yes" *)
module blk_mem_gen_0_blk_mem_gen_v8_4_2
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [5:0]addra;
input [7:0]dina;
output [7:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [5:0]addrb;
input [7:0]dinb;
output [7:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [5:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [7:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [7:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [5:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [5:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
blk_mem_gen_0_blk_mem_gen_v8_4_2_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_2_synth" *)
module blk_mem_gen_0_blk_mem_gen_v8_4_2_synth
(douta,
clka,
addra,
dina,
wea);
output [7:0]douta;
input clka;
input [5:0]addra;
input [7:0]dina;
input [0:0]wea;
wire [5:0]addra;
wire clka;
wire [7:0]dina;
wire [7:0]douta;
wire [0:0]wea;
blk_mem_gen_0_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif

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ip/blk_mem_gen_0/blk_mem_gen_0_sim_netlist.vhdl Normal file
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@ -0,0 +1,900 @@
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
-- Date : Sat Oct 1 00:58:45 2022
-- Host : Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim {C:/Users/Jafari
-- Chen/Desktop/8bits-model-cpu/cpu_bitstream/cpu.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_sim_netlist.vhdl}
-- Design : blk_mem_gen_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end blk_mem_gen_0_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_13\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_21\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_29\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_5\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000203020003000200010302020100020200030102010002020003020000",
INIT_01 => X"0302000300010100030200020002020103010200000202010301030101020003",
INIT_02 => X"0001030103030102020200010100000300000001030200030002000300000100",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000303",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000010201",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "NO_CHANGE",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 11) => B"000",
ADDRARDADDR(10 downto 5) => addra(5 downto 0),
ADDRARDADDR(4 downto 0) => B"00000",
ADDRBWRADDR(13 downto 11) => B"000",
ADDRBWRADDR(10 downto 5) => addra(5 downto 0),
ADDRBWRADDR(4 downto 0) => B"10000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 10) => B"000000",
DIADI(9 downto 8) => dina(3 downto 2),
DIADI(7 downto 2) => B"000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(15 downto 10) => B"000000",
DIBDI(9 downto 8) => dina(7 downto 6),
DIBDI(7 downto 2) => B"000000",
DIBDI(1 downto 0) => dina(5 downto 4),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\,
DOADO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\,
DOADO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\,
DOADO(10) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_5\,
DOADO(9 downto 8) => douta(3 downto 2),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\,
DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\,
DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\,
DOADO(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_13\,
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\,
DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\,
DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\,
DOBDO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\,
DOBDO(10) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_21\,
DOBDO(9 downto 8) => douta(7 downto 6),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\,
DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\,
DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\,
DOBDO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\,
DOBDO(2) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_29\,
DOBDO(1 downto 0) => douta(5 downto 4),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\,
ENARDEN => '1',
ENBWREN => '1',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 2) => B"00",
WEBWE(1) => wea(0),
WEBWE(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end blk_mem_gen_0_blk_mem_gen_prim_width;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.blk_mem_gen_0_blk_mem_gen_prim_wrapper_init
port map (
addra(5 downto 0) => addra(5 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end blk_mem_gen_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.blk_mem_gen_0_blk_mem_gen_prim_width
port map (
addra(5 downto 0) => addra(5 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end blk_mem_gen_0_blk_mem_gen_top;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.blk_mem_gen_0_blk_mem_gen_generic_cstr
port map (
addra(5 downto 0) => addra(5 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_v8_4_2_synth is
port (
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_v8_4_2_synth : entity is "blk_mem_gen_v8_4_2_synth";
end blk_mem_gen_0_blk_mem_gen_v8_4_2_synth;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_v8_4_2_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.blk_mem_gen_0_blk_mem_gen_top
port map (
addra(5 downto 0) => addra(5 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0_blk_mem_gen_v8_4_2 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 5 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 5 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 6;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 6;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "Estimated Power for IP : 2.3883 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "blk_mem_gen_0.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 64;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 64;
attribute C_READ_LATENCY_A : integer;
attribute C_READ_LATENCY_A of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 1;
attribute C_READ_LATENCY_B : integer;
attribute C_READ_LATENCY_B of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 1;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 64;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 64;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "blk_mem_gen_v8_4_2";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_0_blk_mem_gen_v8_4_2 : entity is "yes";
end blk_mem_gen_0_blk_mem_gen_v8_4_2;
architecture STRUCTURE of blk_mem_gen_0_blk_mem_gen_v8_4_2 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.blk_mem_gen_0_blk_mem_gen_v8_4_2_synth
port map (
addra(5 downto 0) => addra(5 downto 0),
clka => clka,
dina(7 downto 0) => dina(7 downto 0),
douta(7 downto 0) => douta(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity blk_mem_gen_0 is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of blk_mem_gen_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of blk_mem_gen_0 : entity is "blk_mem_gen_0,blk_mem_gen_v8_4_2,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of blk_mem_gen_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of blk_mem_gen_0 : entity is "blk_mem_gen_v8_4_2,Vivado 2018.3";
end blk_mem_gen_0;
architecture STRUCTURE of blk_mem_gen_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 6;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 6;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.3883 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "blk_mem_gen_0.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "blk_mem_gen_0.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 64;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 64;
attribute C_READ_LATENCY_A : integer;
attribute C_READ_LATENCY_A of U0 : label is 1;
attribute C_READ_LATENCY_B : integer;
attribute C_READ_LATENCY_B of U0 : label is 1;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 64;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 64;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "NO_CHANGE";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute x_interface_info : string;
attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
begin
U0: entity work.blk_mem_gen_0_blk_mem_gen_v8_4_2
port map (
addra(5 downto 0) => addra(5 downto 0),
addrb(5 downto 0) => B"000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(7 downto 0) => dina(7 downto 0),
dinb(7 downto 0) => B"00000000",
douta(7 downto 0) => douta(7 downto 0),
doutb(7 downto 0) => NLW_U0_doutb_UNCONNECTED(7 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(5 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(5 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(5 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(5 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7 downto 0) => B"00000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;

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// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
// Date : Sat Oct 1 00:58:45 2022
// Host : Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub {C:/Users/Jafari
// Chen/Desktop/8bits-model-cpu/cpu_bitstream/cpu.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.v}
// Design : blk_mem_gen_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_4_2,Vivado 2018.3" *)
module blk_mem_gen_0(clka, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,wea[0:0],addra[5:0],dina[7:0],douta[7:0]" */;
input clka;
input [0:0]wea;
input [5:0]addra;
input [7:0]dina;
output [7:0]douta;
endmodule

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-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018
-- Date : Sat Oct 1 00:58:45 2022
-- Host : Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub {C:/Users/Jafari
-- Chen/Desktop/8bits-model-cpu/cpu_bitstream/cpu.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_0_stub.vhdl}
-- Design : blk_mem_gen_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity blk_mem_gen_0 is
Port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end blk_mem_gen_0;
architecture stub of blk_mem_gen_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,wea[0:0],addra[5:0],dina[7:0],douta[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_2,Vivado 2018.3";
begin
end;

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memory_initialization_radix=2;
memory_initialization_vector=11100000 00101000 11011001 00101000 11101000 00100001 11100010 00001010 11100011 00001010 01001110 11100111 10001110 11000001 00000010 11011101 00101001 11011000 00101001 11001000 00000010 11100010 00010111 11000000 00000001 10100001 11111010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00011001 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 ;

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2018.3:
* Version 8.4 (Rev. 2)
* Feature Enhancement: Read Latency Support added for URAM when selected through IP Integrator
* Other: Power Calculations disabled for URAM primitives in IP GUI, no functional changes
* Other: Internal device family change, no functional changes
2018.2:
* Version 8.4 (Rev. 1)
* No changes
2018.1:
* Version 8.4 (Rev. 1)
* No changes
2017.4:
* Version 8.4 (Rev. 1)
* General: Write depth shown in IP GUI is now dependent on number of BRAMs available in a chosen device, no functional changes
2017.3:
* Version 8.4
* General: Safety Circuit option is enabled by default if reset option in any one port is enabled
2017.2:
* Version 8.3 (Rev. 6)
* No changes
2017.1:
* Version 8.3 (Rev. 6)
* General: Internal device family change, no functional changes
* General: When common_clock is selected clkb is internally connected to clka, but the interface remains same to support the backword compatiability. User make sure of connecting the both the clocks to same clock source when in common_clock mode
2016.4:
* Version 8.3 (Rev. 5)
* General: Fixes for behavioral Model issues when built-IN ECC is enabled (to be consistent with RTL)
2016.3:
* Version 8.3 (Rev. 4)
* Feature Enhancement: URAM addressing updates while calling XPM_Memory when 32-bit addressing is enabled
* Other: Enable support for future devices
* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
2016.2:
* Version 8.3 (Rev. 3)
* updated the IP,not to set WRITE_DEPTH parameter to 8192 everytime when the mode is switched to BRAM_Controller
* Updated the IP to support the device package changes
2016.1:
* Version 8.3 (Rev. 2)
* Updated the IP to deliver only verilog behavioral model
* Updated the IP to support UltraRAM in IP Integrator
* Updated the IP to support the device package changes
2015.4.2:
* Version 8.3 (Rev. 1)
* No changes
2015.4.1:
* Version 8.3 (Rev. 1)
* No changes
2015.4:
* Version 8.3 (Rev. 1)
* Updated the IP to support the device package changes
2015.3:
* Version 8.3
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
* New ports rsta_busy and rstb_busy are added to enable the safety circuitry to minimize the occurrence of BRAM data corruption
* Simulation models are delivered in VHDL only
2015.2.1:
* Version 8.2 (Rev. 5)
* No changes
2015.2:
* Version 8.2 (Rev. 5)
* No changes
2015.1:
* Version 8.2 (Rev. 5)
* Delivering non encrypted behavioral models
* Supported memory depth is increased up to 1M words
* Added the power saving feature (RDADDRCHG) for ultrascale devices
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 8.2 (Rev. 4)
* Updated the IP to support the device package changes
2014.4:
* Version 8.2 (Rev. 3)
* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
* Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices
* Internal device family change, no functional changes
2014.3:
* Version 8.2 (Rev. 2)
* Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used
* Fixed the GUI crash in Simple Dual Port RAM
* Added support of all write modes in Simple Dual Port RAM when ECC is not used
* Increased the supported depth to a maximum value of 256k
2014.2:
* Version 8.2 (Rev. 1)
* Updated the GUI tool tip for Byte write enable in the page-1 of block memory generator GUI
2014.1:
* Version 8.2
* Added support of the cascaded Primitives of widths 1 and 2 for ultra-scale devices
* Added support of the ECCPIPE register in the built-in ecc mode for ultra-scale devices
* Added support of the dynamic power saving for ultra-scale devices
* Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7-series devices
* Internal device family name change, no functional changes
2013.4:
* Version 8.1
* The Primitive output registers are made "ON" by default in the stand alone mode
* Added cascaded support for ultrascale devices to construct 64Kx1 primitive by using two 32Kx1 primitives
* Added support for ultrascale devices
2013.3:
* Version 8.0 (Rev. 2)
* Added parameter "CTRL_ECC_ALGO" for supporting ECC in IP Integrator.
* Improved GUI speed and responsivness, no functional changes
* Reduced synthesis and simulation warnings
* Added support for Cadence IES and Synopsys VCS simulators
* Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN"
* Changed BRAM Interface DIN and DOUT to match bus interface directions.
2013.2:
* Version 8.0 (Rev. 1)
* No Changes
2013.1:
* Version 8.0
* Native Vivado Release
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
(c) Copyright 2002 - 2018 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

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library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_4_2 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_4_2;
architecture xilinx of blk_mem_gen_v8_4_2 is
begin
end
architecture xilinx;

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// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module blk_mem_gen_0 (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [5 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [7 : 0] dina;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [7 : 0] douta;
blk_mem_gen_v8_4_2 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("blk_mem_gen_0.mif"),
.C_INIT_FILE("blk_mem_gen_0.mem"),
.C_USE_DEFAULT_DATA(1),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("NO_CHANGE"),
.C_WRITE_WIDTH_A(8),
.C_READ_WIDTH_A(8),
.C_WRITE_DEPTH_A(64),
.C_READ_DEPTH_A(64),
.C_ADDRA_WIDTH(6),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(8),
.C_READ_WIDTH_B(8),
.C_WRITE_DEPTH_B(64),
.C_READ_DEPTH_B(64),
.C_ADDRB_WIDTH(6),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_READ_LATENCY_A(1),
.C_READ_LATENCY_B(1),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("0"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 2.3883 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(6'B0),
.dinb(8'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(8'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule

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User Configuration
--------------------------------------------------------------------------------
Algorithm : Minimum_Area
Memory Type : Single_Port_RAM
Port A Read Width : [8]
Port A Write Width : [8]
Memory Depth : [64]
----------------------------------------------------------------------------------
Block RAM resource(s) (18K BRAMs) : [1]
Block RAM resource(s) (36K BRAMs) : [0]
----------------------------------------------------------------------------------
Clock A Frequency : [100]
Port A Enable Rate : [100]
Port A Write Rate : [50]
----------------------------------------------------------------------------------
Estimated Power for IP : 2.3883 mW
----------------------------------------------------------------------------------

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-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_4_2;
USE blk_mem_gen_v8_4_2.blk_mem_gen_v8_4_2;
ENTITY blk_mem_gen_0 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_0;
ARCHITECTURE blk_mem_gen_0_arch OF blk_mem_gen_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_4_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_READ_LATENCY_A : INTEGER;
C_READ_LATENCY_B : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_4_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_4_2,Vivado 2018.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_0_arch : ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_4_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_0_arch: ARCHITECTURE IS "blk_mem_gen_0,blk_mem_gen_v8_4_2,{x_ipProduct=Vivado 2018.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.4,x_ipCoreRevision=2,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=blk_m" &
"em_gen_0.mif,C_INIT_FILE=blk_mem_gen_0.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=NO_CHANGE,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=64,C_READ_DEPTH_A=64,C_ADDRA_WIDTH=6,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_" &
"DEPTH_B=64,C_READ_DEPTH_B=64,C_ADDRB_WIDTH=6,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_READ_LATENCY_A=1,C_READ_LATENCY_B=1,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOW" &
"N_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.3883 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_PARAMETER OF clka: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
BEGIN
U0 : blk_mem_gen_v8_4_2
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "blk_mem_gen_0.mif",
C_INIT_FILE => "blk_mem_gen_0.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 0,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "NO_CHANGE",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 64,
C_READ_DEPTH_A => 64,
C_ADDRA_WIDTH => 6,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 64,
C_READ_DEPTH_B => 64,
C_ADDRB_WIDTH => 6,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_READ_LATENCY_A => 1,
C_READ_LATENCY_B => 1,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 2.3883 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => '0',
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_0_arch;

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`timescale 1ns / 1ps
module ALU_tb;
reg clk,rst,IADD,ISUB,IADC,ISBB,IMUL,IDIV,IINC,IDEC,ISHL,ISHR,INOT,INEG,IAND,IOR,IJMP,IJA,IJB,IJE,EALU;
reg [3:0] Tgt1, Tgt2;
reg [7:0] DR0,DR1, DR2,DR3;
reg [7:0]Flags_in;
wire [7:0] Flags_out;
wire [7:0] Dout,Dout_R1;
wire IJ;
ALU u0(clk,rst,Tgt1,Tgt2,DR0,DR1,DR2,DR3,
IADD,ISUB,IADC,ISBB,IMUL,IDIV,IINC,IDEC,ISHL,ISHR,INOT,INEG,IAND,IOR,IJMP,IJA,IJB,IJE,EALU,
Flags_in,Flags_out, Dout,Dout_R1,IJ);
initial begin
clk = 1; rst = 1;
end
initial begin
#10 DR0=8'h20;DR1=8'h21;DR2=8'h22;DR3=8'h23;Flags_in=8'b00000001;
#10 Tgt1=4'b0001;Tgt2=4'b1000;EALU=1;
#10 IADD=1;
#10 IADD=0;ISUB=1;
#10 ISUB=0;IADC=1;
#10 IADC=0;ISBB=1;
#10 ISBB=0;IMUL=1;
#10 IMUL=0;IDIV=1;
#10 IDIV=0;INOT=1;
#10 INOT=0;INEG=1;
#10 INEG=0;IAND=1;
#10 IAND=0;IOR=1;
#10 IOR=0;
#10 DR0=8'h20;DR1=8'h21;DR2=8'h22;DR3=8'h1;Flags_in=8'b00000001;
#10 ISHL=1;
#10 ISHL=0;ISHR=1;
#10 ISHR=0;
#10 IJMP=1;
#10 IJMP=0;IJA=1;
#10 $stop;
end
endmodule

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`timescale 1ns / 1ps
module Controller_tb;
reg clk,rst;
reg [27:0] ctrl;
reg [3:0] Tgt1,Tgt2;
wire [7:0] T;
wire IA,IB,IADD,ISUB,IADC,ISBB,IMUL,IDIV,
IINC,IDEC,ISHL,ISHR,INOT,INEG,IAND,IOR,
IJMP,IJA,IJB,IJE,EALU,I0,E0,I1,E1,I2,E2,I3,E3,IF,EF,
IDFR,IDFB,EDTB,iwr,IPC,IMPC,IMAR,IIR,IMARB;
Controller u0(ctrl,
Tgt1,Tgt2,
T,
IA,IB,IADD,ISUB,IADC,ISBB,IMUL,IDIV,
IINC,IDEC,ISHL,ISHR,INOT,INEG,IAND,IOR,
IJMP,IJA,IJB,IJE,EALU,I0,E0,I1,E1,I2,E2,I3,E3,IF,EF,
IDFR,IDFB,EDTB,iwr,IPC,IMPC,IMAR,IIR,IMARB) ;
SG u1(clk,rst,T);
initial begin
clk = 1'b1;
rst=1;
end
always #5 clk = ~clk;
initial begin
#80 ctrl=28'b0000_0000_0000_1000_0000_0000_0000;Tgt1=4'b0001;Tgt2=4'b1000;
#80 ctrl=28'b0000_0000_0000_0000_0010_0000_0000;Tgt1=4'b0001;Tgt2=4'b0000;
#80 ctrl=28'b0010_0000_0000_0000_0000_0000_0000;Tgt1=4'b0001;Tgt2=4'b0000;
#80 ctrl=28'b0000_0000_0000_0001_0000_0000_0000;Tgt1=4'b0001;Tgt2=4'b0000;
#80 ctrl=28'b0000_0000_0000_0000_0000_0000_0001;Tgt1=4'b0000;Tgt2=4'b0000;
end
endmodule

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`timescale 1ns / 1ps
module Decoder_tb;
reg [7:0] cmd;
wire [27:0] res;
wire [3:0] Tgt1, Tgt2;
Decoder dut(cmd,res,Tgt1,Tgt2);
initial begin
#10 cmd=8'b00000000;
#10 cmd=8'b00000001;
#10 cmd=8'b00000010;
#10 cmd=8'b11000000;
#10 cmd=8'b11000101;
#10 cmd=8'b11001010;
#10 cmd=8'b11001111;
#10 cmd=8'b11010000;
#10 cmd=8'b11010101;
#10 cmd=8'b11011010;
#10 cmd=8'b11011111;
#10 cmd=8'b11100000;
#10 cmd=8'b11100101;
#10 cmd=8'b11101010;
#10 cmd=8'b00011100;
#10 cmd=8'b00100011;
#10 cmd=8'b00111011;
#10 cmd=8'b01000100;
#10 cmd=8'b01010100;
#10 cmd=8'b01101010;
#10 cmd=8'b01110011;
#10 cmd=8'b10001010;
#10 cmd=8'b10011111;
#10 cmd=8'b10100000;
#10 $stop;
end
endmodule

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`timescale 1ns / 1ps
module LS377_tb;
reg CLK;
reg rst;
reg EN;
reg [7:0] D;
wire [7:0] Q;
LS377 DUT(
.clk(CLK),
.rst(rst),
.EN(EN),
.D(D),
.Q(Q)
);
initial begin
CLK = 1'b1;
rst=1;
EN=0;
end
always #5 CLK = ~CLK;
initial begin
#10 D=8'd12; EN=0;
#10 D=8'd13; EN=1;
#10 D=8'd14; EN=0;
#10 D=8'd15;
#10 D=8'd16; EN=1;
#10 D=8'd17;
#10 D=8'd18; EN=0;
#10 D=8'd19;
#10 D=8'd20;rst=0;
#10 D=8'd21;rst=1;
#10 D=8'd22;EN=1;
#10 $stop;
end
endmodule

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`timescale 1ns / 1ps
module MAR_tb;
reg clk, IMAR, IMARB;
reg[5:0] Din;//PC计数器传来的地址
reg [7:0] DinD;//PC计数器传来的地址
reg rst;
wire [5:0] Dout;
MAR u0(clk, IMAR, IMARB,
Din,DinD, rst, Dout);
initial begin
clk = 1'b1;
rst=0;
end
always #5 clk=~clk;
initial begin
#10 rst=1;
#10 Din=6'd12; DinD=8'd33; IMAR=1;IMARB=0;
#10 Din=6'd13; DinD=8'd34; IMAR=0;
#10 Din=6'd14; DinD=8'd35; IMAR=1;
#10 Din=6'd15; DinD=8'd36; IMARB=1;IMAR=0;
#10 Din=6'd16; DinD=8'd37; IMARB=0;
#10 Din=6'd17; DinD=8'd38; IMARB=1;
#10 $stop;
end
endmodule

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`timescale 1ns / 1ps
module Mux_tb();
reg [7:0] D1,D2;
reg ctrl;
wire [7:0] Dout;
MUX u0(D1,D2,ctrl,Dout);
initial begin
#10 D1=8'd11;D2=8'd21;
#10 D1=8'd12;D2=8'd22;ctrl=1;
#10 D1=8'd13;D2=8'd23;
#10 D1=8'd14;D2=8'd24;ctrl=0;
#10 D1=8'd15;D2=8'd25;
#10 D1=8'd16;D2=8'd26;ctrl=1;
#10 $stop;
end
endmodule

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`timescale 1ns / 1ps
module PC_tb(
);
reg clk,IPC, IMPC, rst,IJ;
reg [7:0] Din;
wire [5:0] Dout;
PC u0(
.clk(clk),
.IPC(IPC),
.IMPC(IMPC),
.IJ(IJ),
.rst(rst),
.Din(Din),
.Dout(Dout)
);
initial begin
clk = 1'b1;
rst=0;
end
always #5 clk=~clk;
initial begin
#10 rst=1;
#10 IPC=1;
#10 IPC=1;
#10 IPC=1;
#10 IMPC=1; Din=6'h11;
#10 IMPC=1;IJ=1;IPC=0;Din=6'h15;
#10 IPC=1;IMPC=0;IJ=0;
#10 IMPC=1;IJ=1;IPC=0; Din=6'h20;
#10 IPC=1;IMPC=0;IJ=0;
#10 IPC=1;IMPC=0;
#10 $stop;
end
endmodule

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`timescale 1ns / 1ps
module RA_tb(
);
reg clk,rst,I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL,IDIV;
reg [7:0] Din,Din_Low, Flags_in;
wire [7:0] Dout0, Flags_out;
wire [7:0] DR0, DR1, DR2, DR3;
RA u0(
.clk(clk),
.rst(rst),
.I0(I0),
.E0(E0),
.I1(I1),
.E1(E1),
.I2(I2),
.E2(E2),
.I3(I3),
.E3(E3),
.IF(IF),
.EF(EF),
.IMUL(IMUL),
.IDIV(IDIV),
.Din(Din),
.DinA(Din_Low),
.Flags_in(Flags_in),
.Dout0(Dout0),
.Flags_out(Flags_out),
.DR0(DR0),
.DR1(DR1),
.DR2(DR2),
.DR3(DR3)
);
initial begin
clk = 1'b1;
rst=1;
{I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0000_000;IDIV=0;
end
always #5 clk = ~clk;
initial begin
#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b1000_0000_000;Din = 8'd12;IDIV=0;
#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0100_0000_000;Din = 8'd13;
#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0010_0000_000;Din = 8'd14;
#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0001_0000_000;Din = 8'd15;
#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_1000_000;
#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0100_000;
#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0010_000;
#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0001_000;
#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0000_001;Din_Low = 8'd21;
#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0100_000;Din = 8'd20;
#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0000_100;Flags_in = 8'd23;
#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0000_010;
#10 $stop;
end
endmodule

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`timescale 1ns / 1ps
module SG_tb;
reg CLK;
reg rst;
wire [7:0] signals;
SG DUT(
.clk(CLK),
.rst(rst),
.signals(signals)
);
initial begin
CLK = 1; rst = 0;
end
always #5 CLK=~CLK;
initial begin
#10 rst=1;
end
endmodule

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`timescale 1ns / 1ps
module Tri_tb(
);
reg [7:0] din;
reg en;
wire [7:0] dout;
Tri u0(din,en,dout);
initial begin
#10 din=8'd11; en=1;
#10 din=8'd12; en=1;
#10 din=8'd13; en=0;
#10 din=8'd14; en=0;
#10 din=8'd15; en=0;
#10 din=8'd16; en=1;
#10 din=8'd17; en=1;
#10 din=8'd18; en=1;
#5 $stop;
end
endmodule

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`timescale 1ns / 1ps
module cpu_tb;
reg clk,rst;
wire [7:0] bus,ram;
wire [5:0] MAR;
wire [27:0] ctrl_signal;
wire [7:0] R0,R1,R2,R3;
wire HALT;
cpu DUT(clk,rst,
bus,ram,
MAR, ctrl_signal,
R0,R1,R2,R3,HALT);
initial begin
#5 rst=0;clk=1;
#10 rst=1;
#10 rst=0;
#55
#10 rst=1;
end
always #5 clk=~clk;
endmodule

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`timescale 1ns / 1ps
module dbus_tb;
reg [7:0] DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus;
wire [7:0] bus_A,bus_B,bus_IR,bus_PC;
dbus DUT(DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus,bus_A,bus_B,bus_IR,bus_PC);
initial begin
#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'dZ,8'dZ,8'dZ,8'dZ,8'dZ,8'dZ};
#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'd12,8'dZ,8'dZ,8'dZ,8'dZ,8'dZ};
#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'dZ,8'd23,8'dZ,8'dZ,8'dZ,8'dZ};
#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'dZ,8'dZ,8'd55,8'dZ,8'dZ,8'dZ};
#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'dZ,8'dZ,8'dZ,8'd1,8'dZ,8'dZ};
#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'dZ,8'dZ,8'dZ,8'dZ,8'd33,8'dZ};
#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'dZ,8'dZ,8'dZ,8'dZ,8'dZ,8'd4};
#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'd123,8'd231,8'dZ,8'dZ,8'dZ,8'dZ};
#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'd1,8'd2,8'dZ,8'dZ,8'dZ,8'dZ};
#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'bZZZZ_ZZZ1,8'bZZZZ_ZZ1Z,8'b1111_ZZZZ,8'dZ,8'dZ,8'dZ};
#5 $stop;
end
endmodule

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`timescale 1ns/10ps
module ram_ip_tb();
reg we,clk,EDTB;
reg [5:0] addr;
reg [7:0] data_in;
wire [7:0] data_out;
wire [7:0] DR_MAR;
ram_ip DUT(
.iwr (we),
.clk (clk),
.EDTB(EDTB),
.addr (addr),
.din (data_in),
.dout (data_out),
.to_MAR(DR_MAR)
);
initial begin
#20 we = 1'b0;EDTB=1;clk = 1'b0;addr = 6'd0;
end
always #10 clk = ~ clk;
initial begin
#20 we = 1'b0;
#20 addr = 6'd0;
#20 addr = 6'd1;
#20 addr = 6'd2;
#20 addr = 6'd3;
#20 addr = 6'd4;
#20 addr = 6'd5;
#20 we = 1'b1; addr = 6'd0; data_in = 8'h3e;
#20 addr = 6'd1; data_in = 8'h6;
#20 addr = 6'd2; data_in = 8'hc6;
#20 addr = 6'd3; data_in = 8'h7;
#20 addr = 6'd4; data_in = 8'h76;
#20 addr = 6'd5; data_in = 8'b0000_0000;
#20 addr = 6'd6; data_in = 8'bxxxx_xxxx;
#20 we = 1'b0;
#20 addr = 6'd6;
#20 addr = 6'd5;
#20 addr = 6'd4;
#20 addr = 6'd3;
#20 addr = 6'd2;
#20 addr = 6'd1;
#20 $stop;
end
endmodule

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`timescale 1ns / 1ps
module ALU(
input wire clk,//clock
input wire rst,
input wire [3:0] Tgt1,
input wire [3:0] Tgt2,
input wire [7:0] DR0,
input wire [7:0] DR1,
input wire [7:0] DR2,
input wire [7:0] DR3,
input wire IADD,
input wire ISUB,
input wire IADC,
input wire ISBB,
input wire IMUL,//0高八位，1第八位
input wire IDIV,//0存结果，1存余数
input wire IINC,
input wire IDEC,
input wire ISHL,
input wire ISHR,
input wire INOT,
input wire INEG,
input wire IAND,
input wire IOR,
input wire IJMP,
input wire IJA,
input wire IJB,
input wire IJE,
input wire EALU,
input wire [7:0] Flags_in,
output wire [7:0] Flags_out,
output wire [7:0] Dout,
output wire [7:0] Dout_R1,
output reg IJ
);
wire [7:0] DA,DB;//A和B传入ALU的数据
reg [15:0] result; //运算结果
wire EFLAG;//是否传入Flag中 ,是否影响标志位
wire [7:0] Flags;//标志位结果
reg CF,PF,ZF,SF,OF;
//reg IJ;
assign Flags={3'b000,OF,SF,ZF,PF,CF};
assign EFLAG=1;
//wire [15:0] res;
//assign res = result;
//assign test_result=result; //test
//reg [7:0] OA,OB;//乘法特殊处理
//wire op;
//assign op = OA[7]^OB[7];
always @ (*) begin
// if(DA[7]==1'b1) OA={1'b1,~DA[6:0]};
// else OA=DA;
// if(DB[7]==1'b1) OB={1'b1,~DB[6:0]};
// else OB=DB;
if(IADD == 1'b1) begin
result = DA + DB;
CF = result[8];
ZF=~(result[0]||result[1] || result[2] ||result[3] || result[4] || result[5] || result[6] ||result[7]);
PF=~(((result[0]^result[1])^(result[2]^result[3]))^((result[4]^result[5])^(result[6]^result[7])));
SF=result[7];
if((DA[7]^~DB[7])&(result[7]^DB[7])==1) OF=1;
else OF=0;
IJ=1;
end
else if(IADC == 1'b1) begin
result = DA + DB + Flags_in[0];
CF = result[8];
ZF=~(result[0]||result[1] || result[2] ||result[3] || result[4] || result[5] || result[6] ||result[7]);
PF=~(((result[0]^result[1])^(result[2]^result[3]))^((result[4]^result[5])^(result[6]^result[7])));
SF=result[7];
if((DA[7]^~DB[7])&(result[7]^DB[7])==1) OF=1;
else OF=0;
IJ=1;
end
else if(ISUB == 1'b1) begin
result = DA - DB;
if(DA<DB) CF=1;
else CF=0;
ZF=~(result[0]||result[1] || result[2] ||result[3] || result[4] || result[5] || result[6] ||result[7]);
PF=~(((result[0]^result[1])^(result[2]^result[3]))^((result[4]^result[5])^(result[6]^result[7])));
SF=result[7];
if(~(DA[7]^DB[7])&~(result[7]^~DB[7])==1) OF=1;
else OF=0;
IJ=1;
end
else if(ISBB == 1'b1) begin
result = DA - DB - Flags_in[0];
if(DA<(DB+Flags_in[0])) CF=1;
else CF=0;
ZF=~(result[0]||result[1] || result[2] ||result[3] || result[4] || result[5] || result[6] ||result[7]);
PF=~(((result[0]^result[1])^(result[2]^result[3]))^((result[4]^result[5])^(result[6]^result[7])));
SF=result[7];
if(~(DA[7]^DB[7])&~(result[7]^~DB[7])==1) OF=1;
else OF=0;
IJ=1;
end
else if(IMUL==1'b1) begin
result = DA * DB;
if(result[15:8]==8'b0000_0000) CF=0;
else CF=1;
result={result[7:0],result[15:8]};
ZF=Flags_in[2];
PF=Flags_in[1];
SF=Flags_in[3];
OF=CF;
IJ=1;
end
else if(IDIV==1'b1) begin
result[7:0] = DA/DB;
result[15:8]=DA%DB;
CF=Flags_in[0];
ZF=Flags_in[2];
PF=Flags_in[1];
SF=Flags_in[3];
OF=Flags_in[4];
IJ=1;
end
else if(IINC==1'b1) begin
result = DA + 1;
CF=Flags_in[0];
ZF=~(result[0] && result[1] && result[2] &&result[3] && result[4] && result[5] && result[6] &&result[7]);
PF=~(((result[0]^result[1])^(result[2]^result[3]))^((result[4]^result[5])^(result[6]^result[7])));
SF=result[7];
OF=0;
IJ=1;
end
else if(IDEC==1'b1) begin
result = DA - 1;
CF=Flags_in[0];
ZF=~(result[0] && result[1] && result[2] &&result[3] && result[4] && result[5] && result[6] &&result[7]);
PF=~(((result[0]^result[1])^(result[2]^result[3]))^((result[4]^result[5])^(result[6]^result[7])));
SF=result[7];
OF=0;
IJ=1;
end
else if(IOR==1) begin
result[15:8]=8'd0;
result[7:0] = DA|DB;
CF=0;
ZF=~(result[0] && result[1] && result[2] &&result[3] && result[4] && result[5] && result[6] &&result[7]);
PF=~(((result[0]^result[1])^(result[2]^result[3]))^((result[4]^result[5])^(result[6]^result[7])));
SF=result[7];
OF=0;
IJ=1;
end
else if(IAND==1) begin
result[15:8]=8'd0;
result[7:0] = DA&DB;
CF=0;
ZF=~(result[0] && result[1] && result[2] &&result[3] && result[4] && result[5] && result[6] &&result[7]);
PF=~(((result[0]^result[1])^(result[2]^result[3]))^((result[4]^result[5])^(result[6]^result[7])));
SF=result[7];
OF=0;
IJ=1;
end
else if(ISHL==1)begin
result[15:8]=8'd0;
{CF,result[7:0]}=DA<<DB;
ZF=~(result[0] && result[1] && result[2] &&result[3] && result[4] && result[5] && result[6] &&result[7]);
PF=~(((result[0]^result[1])^(result[2]^result[3]))^((result[4]^result[5])^(result[6]^result[7])));
SF=result[7];
OF=0;
IJ=1;
end
else if(ISHR==1)begin
result[15:8]=8'd0;
result[7:0]=DA>>DB;
if(DB>8)
CF=0;
else
CF=DA[DB-1];
ZF=~(result[0]||result[1] || result[2] ||result[3] || result[4] || result[5] || result[6] ||result[7]);
PF=~(((result[0]^result[1])^(result[2]^result[3]))^((result[4]^result[5])^(result[6]^result[7])));
SF=result[7];
OF=0;
IJ=1;
end
else if(INOT==1) begin
result[15:8]=8'd0;
result[7:0] = ~DA;
CF=Flags_in[0];
ZF=Flags_in[2];
PF=Flags_in[1];
SF=Flags_in[3];
OF=Flags_in[4];
IJ=1;
end
else if(INEG==1) begin
result[15:8]=8'd0;
result[7:0]=~DA[7:0];
result[7:0]=result+1;
CF=DA[0]||DA[1] || DA[2] ||DA[3]||DA[4] ||DA[5]|| DA[6] ||DA[7];
ZF=Flags_in[2];
PF=Flags_in[1];
SF=Flags_in[3];
OF = DA[7]&&~(DA[0]||DA[1] || DA[2] ||DA[3]||DA[4] ||DA[5]|| DA[6]);
IJ=1;
end
else if(IJMP==1||IJA==1||IJE==1||IJB==1)
begin
CF=Flags_in[0];
ZF=Flags_in[2];
PF=Flags_in[1];
SF=Flags_in[3];
OF=Flags_in[4];
result[15:8]=8'd0;
result[7:0] = DA[7:0];
if(IJMP==1) begin
IJ=1;
end
else if(IJA==1)begin
if(CF==0&&ZF==0)
IJ=1;
else IJ=0;
end
else if(IJB==1) begin
if(CF==1)
IJ=1;
else IJ=0;
end
else if(IJE==1) begin
if(ZF==1)
IJ=1;
else IJ=0;
end
else begin
IJ=0;
end
end
else begin
result=16'd0;
CF=Flags_in[0];
ZF=Flags_in[2];
PF=Flags_in[1];
SF=Flags_in[3];
OF=Flags_in[4];
IJ=1;
end
// Flags[4:0]={OF,SF,ZF,PF,CF};
// Flags[7:5]=3'd0;
// EFLAG=1'b1;//...................
end
MUX_ALU u0(
.Tgt1(Tgt1),
.Tgt2(Tgt2),
.DR0(DR0),
.DR1(DR1),
.DR2(DR2),
.DR3(DR3),
.DA(DA),
.DB(DB)
);
Tri Tri_BUS(
.din(result[7:0]),
.en(EALU&&IJ),
.dout(Dout)
);
Tri Tri_R1(
.din(result[15:8]),
.en(IMUL||IDIV),
.dout(Dout_R1)
);
Tri Tri_Flag(
.din(Flags),
.en(EFLAG),
.dout(Flags_out)
);
endmodule

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`timescale 1ns / 1ps
module Controller(
input wire [27:0] ctrl,
input wire [3:0] Tgt1,
input wire [3:0] Tgt2,
input wire [7:0] T,
output wire IA,IB,IADD,ISUB,IADC,ISBB,IMUL,IDIV,
IINC,IDEC,ISHL,ISHR,INOT,INEG,IAND,IOR,
IJMP,IJA,IJB,IJE,EALU,I0,E0,I1,E1,I2,E2,I3,E3,IF,EF,
IDFR,IDFB,EDTB,iwr,IPC,IMPC,IMAR,IIR,IMARB
);
assign IADD=T[6]&&(ctrl[3]||ctrl[15]) ;
assign ISUB=T[6]&&(ctrl[5]||ctrl[17]||ctrl[23]) ;
assign IADC=T[6]&&(ctrl[4]||ctrl[16]) ;
assign ISBB=T[6]&&(ctrl[6]||ctrl[18]) ;
assign IMUL=T[6]&&(ctrl[1]||ctrl[7]) ;
assign IDIV=T[6]&&(ctrl[2]||ctrl[8]) ;
assign IINC=0 ;
assign IDEC=0 ;
assign ISHL=T[6]&&ctrl[19] ;
assign ISHR=T[6]&&ctrl[20] ;
assign INOT=T[6]&&ctrl[12] ;
assign INEG=T[6]&&ctrl[13] ;
assign IAND=T[6]&&ctrl[21] ;
assign IOR=T[6]&&ctrl[22] ;
assign IJMP=T[6]&&ctrl[24] ;
assign IJA=T[6]&&ctrl[25] ;
assign IJB=T[6]&&ctrl[26] ;
assign IJE=T[6]&&ctrl[27] ;
assign EALU=T[6]&&
(ctrl[1]||ctrl[2]||ctrl[3]||ctrl[4]||ctrl[5]||ctrl[6]||ctrl[7]
||ctrl[8]||ctrl[12]||ctrl[13]||ctrl[15]||ctrl[16]||ctrl[17]||ctrl[18]||ctrl[19]||ctrl[20]||ctrl[21]||ctrl[22]||ctrl[24]||ctrl[25]||ctrl[26]||ctrl[27]) ;
assign I0=(Tgt1[0]&&T[7]&&(ctrl[1]||ctrl[2]||ctrl[3]||ctrl[4]||ctrl[5]||ctrl[6]||ctrl[7]||ctrl[8]||ctrl[9]
||ctrl[12]||ctrl[13]||ctrl[15]||ctrl[16]||ctrl[17]||ctrl[18]||ctrl[19]||ctrl[20]||ctrl[21]||ctrl[22]))
||(Tgt1[0]&&T[6]&&ctrl[11])
||(Tgt1[0]&&T[4]&&ctrl[14]) ;
assign E0=(Tgt1[0]&&T[6]&&ctrl[10])||(Tgt2[0]&&T[3]&&ctrl[14]) ;
assign I1=(Tgt1[1]&&T[7]&&(ctrl[1]||ctrl[2]||ctrl[3]||ctrl[4]||ctrl[5]||ctrl[6]||ctrl[7]||ctrl[8]||ctrl[9]
||ctrl[12]||ctrl[13]||ctrl[15]||ctrl[16]||ctrl[17]||ctrl[18]||ctrl[19]||ctrl[20]||ctrl[21]||ctrl[22]))
||(Tgt1[1]&&T[6]&&ctrl[11])
||(Tgt1[1]&&T[4]&&ctrl[14]) ;
assign E1=(Tgt1[1]&&T[6]&&ctrl[10])||(Tgt2[1]&&T[3]&&ctrl[14]) ;
assign I2=(Tgt1[2]&&T[7]&&(ctrl[1]||ctrl[2]||ctrl[3]||ctrl[4]||ctrl[5]||ctrl[6]||ctrl[7]||ctrl[8]||ctrl[9]
||ctrl[12]||ctrl[13]||ctrl[15]||ctrl[16]||ctrl[17]||ctrl[18]||ctrl[19]||ctrl[20]||ctrl[21]||ctrl[22]))
||(Tgt1[2]&&T[6]&&ctrl[11])
||(Tgt1[2]&&T[4]&&ctrl[14]) ;
assign E2=(Tgt1[2]&&T[6]&&ctrl[10])||(Tgt2[2]&&T[3]&&ctrl[14]) ;
assign I3=(Tgt1[3]&&T[7]&&(ctrl[1]||ctrl[2]||ctrl[3]||ctrl[4]||ctrl[5]||ctrl[6]||ctrl[7]||ctrl[8]||ctrl[9]
||ctrl[12]||ctrl[13]||ctrl[15]||ctrl[16]||ctrl[17]||ctrl[18]||ctrl[19]||ctrl[20]||ctrl[21]||ctrl[22]))
||(Tgt1[3]&&T[6]&&ctrl[11])
||(Tgt1[3]&&T[4]&&ctrl[14]) ;
assign E3=(Tgt1[3]&&T[6]&&ctrl[10])||(Tgt2[3]&&T[3]&&ctrl[14]) ;
assign IF=T[7]&&(ctrl[1]||ctrl[2]||ctrl[3]||ctrl[4]||ctrl[5]||ctrl[6]||ctrl[7]||ctrl[8]
||ctrl[15]||ctrl[16]||ctrl[17]||ctrl[18]||ctrl[19]||ctrl[20]||ctrl[21]||ctrl[22]||ctrl[23]) ;
assign EF=1 ;
//assign IDFR=T[1]||(T[4]&&(ctrl[1]||ctrl[2]||ctrl[3]||ctrl[4]||ctrl[5]||ctrl[6]||ctrl[9]||ctrl[10]||ctrl[11]))
// ||(T[6]&&ctrl[9]) ;
//assign IDFB=T[7]&&ctrl[10] ;
assign EDTB=(T[2]||(T[5]&&ctrl[11])||(T[6]&&(ctrl[9])))&&~ctrl[0] ;
assign iwr=T[6]&&ctrl[10];
assign IPC=(T[2]||(T[5]&&(ctrl[1]||ctrl[2]||ctrl[3]||ctrl[4]||ctrl[5]||ctrl[6]||ctrl[9]
||ctrl[10]||ctrl[11])) )&&~ctrl[0] ;
assign IMPC=T[6]&&(ctrl[24]||ctrl[25]||ctrl[26]||ctrl[27]) ;
assign IMAR=(T[0]||(T[3]&&(ctrl[3]||ctrl[4]||ctrl[5]||ctrl[6]||ctrl[1]||ctrl[2]||ctrl[9]||ctrl[10]||ctrl[11])) )&&~ctrl[0] ;
assign IIR=T[2]&&~ctrl[0] ;
assign IMARB=T[5]&&(ctrl[9]||ctrl[10]) ;
endmodule

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`timescale 1ns / 1ps
module Decoder(
input wire [7:0] cmd,
output wire [27:0] res,//xxxxxxxxxxxxxx
output wire [3:0] Tgt1,
output wire [3:0] Tgt2
);
wire [1:0] re1,re2;
assign res[0]=~cmd[7]&~cmd[6]&~cmd[5]&~cmd[4]&cmd[3]&cmd[2]&cmd[1]&cmd[0];
assign res[1]=~cmd[7]&~cmd[6]&~cmd[5]&~cmd[4]&~cmd[3]&~cmd[2]&~cmd[1]&cmd[0];
assign res[2]=~cmd[7]&~cmd[6]&~cmd[5]&~cmd[4]&~cmd[3]&~cmd[2]&cmd[1]&~cmd[0];
assign res[3]=cmd[7]&cmd[6]&~cmd[5]&~cmd[4]&~cmd[3]&~cmd[2];
assign res[4]=cmd[7]&cmd[6]&~cmd[5]&~cmd[4]&~cmd[3]&cmd[2];
assign res[5]=cmd[7]&cmd[6]&~cmd[5]&~cmd[4]&cmd[3]&~cmd[2];
assign res[6]=cmd[7]&cmd[6]&~cmd[5]&~cmd[4]&cmd[3]&cmd[2];
assign res[7]=cmd[7]&cmd[6]&~cmd[5]&cmd[4]&~cmd[3]&~cmd[2];
assign res[8]=cmd[7]&cmd[6]&~cmd[5]&cmd[4]&~cmd[3]&cmd[2];
assign res[9]=cmd[7]&cmd[6]&~cmd[5]&cmd[4]&cmd[3]&~cmd[2];
assign res[10]=cmd[7]&cmd[6]&~cmd[5]&cmd[4]&cmd[3]&cmd[2];
assign res[11]=cmd[7]&cmd[6]&cmd[5]&~cmd[4]&~cmd[3]&~cmd[2];
assign res[12]=cmd[7]&cmd[6]&cmd[5]&~cmd[4]&~cmd[3]&cmd[2];
assign res[13]=cmd[7]&cmd[6]&cmd[5]&~cmd[4]&cmd[3]&~cmd[2];
assign res[14]=~cmd[7]&~cmd[6]&~cmd[5]&cmd[4];
assign res[15]=~cmd[7]&~cmd[6]&cmd[5]&~cmd[4];
assign res[16]=~cmd[7]&~cmd[6]&cmd[5]&cmd[4];
assign res[17]=~cmd[7]&cmd[6]&~cmd[5]&~cmd[4];
assign res[18]=~cmd[7]&cmd[6]&~cmd[5]&cmd[4];
assign res[19]=~cmd[7]&cmd[6]&cmd[5]&~cmd[4];
assign res[20]=~cmd[7]&cmd[6]&cmd[5]&cmd[4];
assign res[21]=cmd[7]&~cmd[6]&~cmd[5]&~cmd[4];
assign res[22]=cmd[7]&~cmd[6]&~cmd[5]&cmd[4];
assign res[23]=cmd[7]&~cmd[6]&cmd[5]&~cmd[4];
assign res[24]=cmd[7]&cmd[6]&cmd[5]&cmd[4]&~cmd[3]&~cmd[2];
assign res[25]=cmd[7]&cmd[6]&cmd[5]&cmd[4]&~cmd[3]&cmd[2];
assign res[26]=cmd[7]&cmd[6]&cmd[5]&cmd[4]&cmd[3]&~cmd[2];
assign res[27]=cmd[7]&cmd[6]&cmd[5]&cmd[4]&cmd[3]&cmd[2];
assign re1[0] = (res[0]||res[1]||res[2])? 1'bZ:((res[3]||res[4]||res[5]||res[6]||res[7]||res[8]||res[9]||res[10]||res[11]||res[12]||res[13]||res[24]||res[25]||res[26]||res[27])&cmd[0])|
((res[14]||res[15]||res[16]||res[17]||res[18]||res[19]||res[20]||res[21]||res[22]||res[23])&cmd[2]);
assign re1[1] = (res[0]||res[1]||res[2])? 1'bZ:((res[3]||res[4]||res[5]||res[6]||res[7]||res[8]||res[9]||res[10]||res[11]||res[12]||res[13]||res[24]||res[25]||res[26]||res[27])&cmd[1])|
((res[14]||res[15]||res[16]||res[17]||res[18]||res[19]||res[20]||res[21]||res[22]||res[23])&cmd[3]);
assign re2[0] = (res[0]||res[1]||res[2]||res[3]||res[4]||res[5]||res[6]||res[7]||res[8]||res[9]||res[10]||res[11]||res[12]||res[13]||res[24]||res[25]||res[26]||res[27])? 1'bZ:(res[14]||res[15]||res[16]||res[17]||res[18]||res[19]||res[20]||res[21]||res[22]||res[23])&&cmd[0];
assign re2[1] = (res[0]||res[1]||res[2]||res[3]||res[4]||res[5]||res[6]||res[7]||res[8]||res[9]||res[10]||res[11]||res[12]||res[13]||res[24]||res[25]||res[26]||res[27])? 1'bZ:(res[14]||res[15]||res[16]||res[17]||res[18]||res[19]||res[20]||res[21]||res[22]||res[23])&&cmd[1];
assign Tgt1[3] = re1[1]&re1[0];
assign Tgt1[2] = re1[1]&~re1[0];
assign Tgt1[1] = ~re1[1]&re1[0];
assign Tgt1[0] = ~re1[1]&~re1[0];
assign Tgt2[3] = re2[1]&re2[0];
assign Tgt2[2] = re2[1]&~re2[0];
assign Tgt2[1] = ~re2[1]&re2[0];
assign Tgt2[0] = ~re2[1]&~re2[0];
endmodule

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`timescale 1ns / 1ps
module IR(
input wire clk,
input wire rst,
input wire IIR,
input wire [7:0] Din,
output wire [7:0] Dout
);
LS377 u_IR(
.clk(clk),
.rst(rst),
.EN(IIR),
.D(Din),
.Q(Dout)
);
endmodule

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`timescale 1ns / 1ps
//clk EN1 rst0 D -> Q
module LS377(
input wire clk,
input wire EN,
input wire rst,
input wire [7:0] D,
output wire [7:0] Q,
output wire [7:0] Dshow
);
reg [7:0] data=8'b0000_0000;
assign Q = data;
assign Dshow=data;
always @ (posedge clk or negedge rst) begin
if(rst == 0)
data = 8'b0000_0000;
else if(EN == 1)
data = D;
end
endmodule

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`timescale 1ns / 1ps
module MAR(
input wire clk,
input wire IMAR,
input wire IMARB,
input wire [5:0] Din,//PC计数器传来的地址
input wire [7:0] Din_BUS,//PC计数器传来的地址
input wire rst,
output wire [5:0] Dout
);
reg [5:0] addr=6'b000000;
assign Dout=addr;
always @ (posedge IMAR or posedge IMARB or negedge rst) begin
if(rst==0) addr=6'b000000;
else if(IMAR==1) addr = Din;
else if(IMARB==1) addr = Din_BUS[5:0];
else addr=addr;
end
endmodule

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`timescale 1ns / 1ps
module MUX(
input [7:0] D1,D2,
input ctrl,
output wire [7:0] D
);
assign D[7] = (D1[7]&&~ctrl)|| (D2[7]&&ctrl);
assign D[6] = (D1[6]&&~ctrl)|| (D2[6]&&ctrl);
assign D[5] = (D1[5]&&~ctrl)|| (D2[5]&&ctrl);
assign D[4] = (D1[4]&&~ctrl)|| (D2[4]&&ctrl);
assign D[3] = (D1[3]&&~ctrl)|| (D2[3]&&ctrl);
assign D[2] = (D1[2]&&~ctrl)|| (D2[2]&&ctrl);
assign D[1] = (D1[1]&&~ctrl)|| (D2[1]&&ctrl);
assign D[0] = (D1[0]&&~ctrl)|| (D2[0]&&ctrl);
endmodule

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`timescale 1ns / 1ps
module MUX_ALU(
input wire [3:0] Tgt1,
input wire [3:0] Tgt2,
input wire [7:0] DR0,
input wire [7:0] DR1,
input wire [7:0] DR2,
input wire [7:0] DR3,
output reg [7:0] DA,
output reg [7:0] DB
);
always @(*) begin
if(Tgt1[0]==1)
DA=DR0;
else if(Tgt1[1]==1)
DA=DR1;
else if(Tgt1[2]==1)
DA=DR2;
else if(Tgt1[3]==1)
DA=DR3;
else
DA=8'bZZZZ_ZZZZ;
if(Tgt2[0]==1)
DB=DR0;
else if(Tgt2[1]==1)
DB=DR1;
else if(Tgt2[2]==1)
DB=DR2;
else if(Tgt2[3]==1)
DB=DR3;
else
DB=8'bZZZZ_ZZZZ;
end
endmodule

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`timescale 1ns / 1ps
module PC(
input wire clk,
input wire IPC,
input wire IMPC,
input wire IJ,
input wire rst,
input wire [7:0] Din,
output wire [5:0] Dout
);
reg [5:0] now_addr;
assign Dout=now_addr;
always @ (posedge clk or negedge rst) begin
if(rst==0) now_addr=6'b000000;
else if(IPC==1) now_addr=now_addr+1;
else if(IMPC==1&&IJ==1) now_addr=Din[5:0];
else now_addr=now_addr;
end
endmodule

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`timescale 1ns / 1ps
//Register
module R(
input wire clk,
input wire rst,
input wire IR,
input wire ER,
input wire [7:0] Din,
output wire [7:0] Dout,
output wire [7:0] Dshow
);
wire [7:0] data;
LS377 u0(
.clk(IR),
.rst(rst),
.EN(IR),
.D(Din),
.Q(data),
.Dshow(Dshow)
);
Tri u1(
.din(data),
.en(ER),
.dout(Dout)
);
endmodule

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`timescale 1ns / 1ps
module RA(
input wire clk,//clock
input wire rst,//1->0 negedge clear
input wire I0,
input wire E0,//R0 signal
input wire I1,
input wire E1,//R1 signal
input wire I2,
input wire E2,//R2 signal
input wire I3,
input wire E3,//R3 signal
input wire IF,
input wire EF,//Flags
input wire IMUL,//ctrl signal MUL AUL to R1
input wire IDIV,
input wire [7:0] Din,//R0~R3
input wire [7:0] DinA,//low 8 bit from ALU to R1
input wire [7:0] Flags_in,//Flags in
output wire [7:0] Dout0,
// output wire [7:0] Dout1,
//output wire [7:0] Dout2,
//output wire [7:0] Dout3,//R out
output wire [7:0] Flags_out,//Flags out
output wire [7:0] DR0,
output wire [7:0] DR1,
output wire [7:0] DR2,
output wire [7:0] DR3
);
wire [7:0] Dto_R1;
R r0(
.clk(clk),
.rst(rst),
.IR(I0),
.ER(E0),
.Din(Din),
.Dout(Dout0),
.Dshow(DR0)
);
MUX mux(
.D1(Din),
.D2(DinA),
.ctrl(IMUL||IDIV),
.D(Dto_R1)
);
R r1(
.clk(clk),
.rst(rst),
.IR(IMUL||IDIV||I1),
.ER(E1),
.Din(Dto_R1),
.Dout(Dout0),
.Dshow(DR1)
);
R r2(
.clk(clk),
.rst(rst),
.IR(I2),
.ER(E2),
.Din(Din),
.Dout(Dout0),
.Dshow(DR2)
);
R r3(
.clk(clk),
.rst(rst),
.IR(I3),
.ER(E3),
.Din(Din),
.Dout(Dout0),
.Dshow(DR3)
);
R psw(
.clk(clk),
.rst(rst),
.IR(IF),
.ER(EF),
.Din(Flags_in),
.Dout(Flags_out)
);
endmodule

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`timescale 1ns / 1ps
//½ÚÅÄ·¢ÉúÆ÷ clk rst0
module SG(
input wire clk,
input wire rst,
output wire [7:0] signals
);
reg [7:0] state = 8'b10000000;
assign signals = state;
always @(posedge clk or negedge rst) begin
if(rst == 0)
state = 8'b10000000;
else if(clk==1) begin
state[7:1] <= state[6:0];
state[0] <= state[7];
end
end
//wire [7:0] original;
//assign original = {~rst,rst,rst,rst,rst,rst,rst,rst};
//assign signals[7:0] = (rst&{signals[6:0],signals[7]})|(~rst&original[7:0]) ;
endmodule

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module Tri(
input wire [7:0] din,
input en,
output wire [7:0] dout
);
assign dout[7:0]=en?din[7:0]:8'bZZZZ_ZZZZ;
endmodule

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`timescale 1ns/100ps
module clock_4hz(
input wire CLK,
input wire CLRn,
output reg T4hz );
// ?
reg [25:0] Q_conut;
always @( posedge CLK or negedge CLRn ) begin
if ( ~CLRn ) Q_conut <= 26'd0;
else if ( Q_conut < 26'd12499 )
// else if ( Q_conut < 26'd640 )
Q_conut <= Q_conut + 1;
else Q_conut <= 26'd0;
end
always @ ( posedge CLK or negedge CLRn ) begin
if ( ~CLRn ) T4hz <= 0;
else if( Q_conut == 26'd0 )
T4hz <= ~ T4hz;
end
endmodule

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`timescale 1ns / 1ps
module cpu(
input clk,input rst,
output wire [7:0] bus_DR,DR_bus,//dbusÏß
output wire [5:0] MAR_ram,
output wire [27:0] ctrl_signal ,
output wire [7:0] R0,R1,R2,R3,
output wire HALT
);
assign HALT = ctrl_signal[0];
wire [7:0] R_bus,ALU_bus, bus_A,bus_B,bus_IR,bus_PC,bus_R,bus_MAR;
wire [3:0] Tgt1,Tgt2;
wire [5:0] PC_MAR;
wire [7:0] Flag_ALU,ALU_Flag,ALU_Low8,IR_Decoder;
wire IADD,ISUB,IADC,ISBB,IMUL,IDIV,
IINC,IDEC,ISHL,ISHR,INOT,INEG,IAND,IOR,
IJMP,IJA,IJB,IJE,EALU,I0,E0,I1,E1,I2,E2,I3,E3,IF,EF,
EDTB,iwr,IPC,IMPC,IMAR,IIR,IMARB;
wire [7:0] signals;
assign HALT=ctrl_signal[0];
wire [7:0] ram_MAR;
wire IJ;
//always @(posedge rst or posedge ctrl_signal[0]) begin
// if(ctrl_signal[0]) HALT=1;
// else if(rst) HALT=0;
// else HALT=0;
//end
ALU u0(
.clk(clk),
.rst(rst),
.Tgt1(Tgt1),
.Tgt2(Tgt2),
.DR0(R0),
.DR1(R1),
.DR2(R2),
.DR3(R3),
.IADD(IADD),
.ISUB(ISUB),
.IADC(IADC),
.ISBB(ISBB),
.IMUL(IMUL),
.IDIV(IDIV),
.IINC(IINC),
.IDEC(IDEC),
.ISHL(ISHL),
.ISHR(ISHR),
.INOT(INOT),
.INEG(INEG),
.IAND(IAND),
.IOR(IOR),
.IJMP(IJMP),
.IJA(IJA),
.IJB(IJB),
.IJE(IJE),
.EALU(EALU),
.Flags_in(Flag_ALU),
.Flags_out(ALU_Flag),
.Dout(ALU_bus),
.Dout_R1(ALU_Low8),
.IJ(IJ)
);
RA u1(
.clk(clk),
.rst(rst),
.I0(I0),
.E0(E0),
.I1(I1),
.E1(E1),
.I2(I2),
.E2(E2),
.I3(I3),
.E3(E3),
.IF(IF),
.EF(EF),
.IMUL(IMUL),
.IDIV(IDIV),
.Din(bus_R),
.DinA(ALU_Low8),
.Flags_in(ALU_Flag),
.Dout0(R_bus),
.Flags_out(Flag_ALU),
.DR0(R0),
.DR1(R1),
.DR2(R2),
.DR3(R3)
);
//DR u2(
// .clk(clk),
// .IDFR(IDFR),
// .IDFB(IDFB),
// .EDTB(EDTB),
// .Din_RAM(ram_DR),
// .Din_BUS(bus_DR),
// .rst(rst),
// .Dout_RAM(DR_ram),
// .Dout_BUS(DR_bus)
//);
MAR u3(
.clk(clk),
.IMAR(IMAR),
.IMARB(IMARB),
.Din(PC_MAR),
.Din_BUS(ram_MAR),
.rst(rst),
.Dout(MAR_ram)
);
ram_ip u4(
.clk(clk),
.iwr(iwr),
.EDTB(EDTB),
.addr(MAR_ram),
.din(bus_DR),
.dout(DR_bus),
.to_MAR(ram_MAR)
);
PC u5(
.clk(clk),
.IPC(IPC),
.IMPC(IMPC),
.IJ(IJ),
.rst(rst),
.Din(bus_PC),
.Dout(PC_MAR)
);
dbus u6(
.DR_bus(DR_bus),
.R_bus(R_bus),
.ALU_bus(ALU_bus),
.bus_A(bus_A),
.bus_B(bus_B),
.bus_IR(bus_IR),
.bus_PC(bus_PC),
.bus_MAR(bus_MAR),
.bus_R(bus_R),
.bus_DR(bus_DR)
);
IR u7(
.clk(clk),
.rst(rst),
.IIR(IIR),
.Din(bus_IR),
.Dout(IR_Decoder)
);
Decoder u8(
.cmd(IR_Decoder),
.res(ctrl_signal),//26 updatig
.Tgt1(Tgt1),
.Tgt2(Tgt2)
);
SG u9(
.clk(clk),
.rst(rst),
.signals(signals));
Controller u10(
ctrl_signal,
Tgt1,
Tgt2,
signals,
IA,IB,IADD,ISUB,IADC,ISBB,IMUL,IDIV,
IINC,IDEC,ISHL,ISHR,INOT,INEG,IAND,IOR,
IJMP,IJA,IJB,IJE,EALU,I0,E0,I1,E1,I2,E2,I3,E3,IF,EF,
IDFR,IDFB,EDTB,iwr,IPC,IMPC,IMAR,IIR,IMARB
);
endmodule

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memory_initialization_radix=2;
memory_initialization_vector=11100000
00101000
11011001
00101000
11101000
00100001
11100010
00001010
00000011
00001010
01001110
11100111
10001110
11000001
00000010
11011101
00101001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00011001
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
;

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`timescale 1ns / 1ps
module dbus(
input [7:0] DR_bus,R_bus,ALU_bus,
output wire [7:0] bus_A,bus_B,bus_IR,bus_PC,bus_R,bus_DR,bus_MAR
);
wire [7:0] data;
assign data = DR_bus;
assign data = R_bus;
assign data = ALU_bus;
assign bus_A=data;
assign bus_B=data;
assign bus_IR=data;
assign bus_PC=data;
assign bus_R=data;
assign bus_DR=data;
assign bus_MAR=data;
endmodule

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`timescale 1ns / 1ps
module ram_ip(
input wire clk,iwr,EDTB,
input wire [5:0] addr,
input wire [7:0] din,
output wire [7:0] dout,
output wire [7:0] to_MAR
);
wire [7:0] ram_data;
assign to_MAR=ram_data;
blk_mem_gen_0 ram (
.clka(~clk), // input wire clka
.wea(iwr), // input wire [0 : 0] wea
.addra(addr), // input wire [5 : 0] addra
.dina(din), // input wire [7 : 0] dina
.douta(ram_data) // output wire [7 : 0] douta
);
Tri T(
.din(ram_data),
.en(EDTB),
.dout(dout)
);
endmodule