26 lines
1.1 KiB
Verilog
26 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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module dbus_tb;
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reg [7:0] DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus;
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wire [7:0] bus_A,bus_B,bus_IR,bus_PC;
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dbus DUT(DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus,bus_A,bus_B,bus_IR,bus_PC);
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initial begin
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#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'dZ,8'dZ,8'dZ,8'dZ,8'dZ,8'dZ};
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#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'd12,8'dZ,8'dZ,8'dZ,8'dZ,8'dZ};
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#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'dZ,8'd23,8'dZ,8'dZ,8'dZ,8'dZ};
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#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'dZ,8'dZ,8'd55,8'dZ,8'dZ,8'dZ};
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#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'dZ,8'dZ,8'dZ,8'd1,8'dZ,8'dZ};
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#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'dZ,8'dZ,8'dZ,8'dZ,8'd33,8'dZ};
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#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'dZ,8'dZ,8'dZ,8'dZ,8'dZ,8'd4};
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#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'd123,8'd231,8'dZ,8'dZ,8'dZ,8'dZ};
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#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'd1,8'd2,8'dZ,8'dZ,8'dZ,8'dZ};
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#5 {DR_bus,R0_bus,R1_bus,R2_bus,R3_bus,ALU_bus}={8'bZZZZ_ZZZ1,8'bZZZZ_ZZ1Z,8'b1111_ZZZZ,8'dZ,8'dZ,8'dZ};
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#5 $stop;
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end
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endmodule
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