38 lines
693 B
Verilog
38 lines
693 B
Verilog
`timescale 1ns / 1ps
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module MUX_ALU(
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input wire [3:0] Tgt1,
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input wire [3:0] Tgt2,
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input wire [7:0] DR0,
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input wire [7:0] DR1,
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input wire [7:0] DR2,
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input wire [7:0] DR3,
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output reg [7:0] DA,
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output reg [7:0] DB
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);
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always @(*) begin
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if(Tgt1[0]==1)
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DA=DR0;
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else if(Tgt1[1]==1)
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DA=DR1;
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else if(Tgt1[2]==1)
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DA=DR2;
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else if(Tgt1[3]==1)
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DA=DR3;
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else
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DA=8'bZZZZ_ZZZZ;
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if(Tgt2[0]==1)
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DB=DR0;
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else if(Tgt2[1]==1)
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DB=DR1;
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else if(Tgt2[2]==1)
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DB=DR2;
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else if(Tgt2[3]==1)
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DB=DR3;
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else
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DB=8'bZZZZ_ZZZZ;
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end
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endmodule
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