32 lines
399 B
Verilog
32 lines
399 B
Verilog
`timescale 1ns / 1ps
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//Register
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module R(
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input wire clk,
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input wire rst,
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input wire IR,
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input wire ER,
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input wire [7:0] Din,
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output wire [7:0] Dout,
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output wire [7:0] Dshow
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);
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wire [7:0] data;
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LS377 u0(
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.clk(IR),
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.rst(rst),
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.EN(IR),
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.D(Din),
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.Q(data),
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.Dshow(Dshow)
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);
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Tri u1(
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.din(data),
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.en(ER),
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.dout(Dout)
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);
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endmodule
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