185 lines
3.0 KiB
Verilog
185 lines
3.0 KiB
Verilog
`timescale 1ns / 1ps
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module cpu(
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input clk,input rst,
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output wire [7:0] bus_DR,DR_bus,//dbusÏß
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output wire [5:0] MAR_ram,
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output wire [27:0] ctrl_signal ,
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output wire [7:0] R0,R1,R2,R3,
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output wire HALT
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);
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assign HALT = ctrl_signal[0];
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wire [7:0] R_bus,ALU_bus, bus_A,bus_B,bus_IR,bus_PC,bus_R,bus_MAR;
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wire [3:0] Tgt1,Tgt2;
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wire [5:0] PC_MAR;
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wire [7:0] Flag_ALU,ALU_Flag,ALU_Low8,IR_Decoder;
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wire IADD,ISUB,IADC,ISBB,IMUL,IDIV,
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IINC,IDEC,ISHL,ISHR,INOT,INEG,IAND,IOR,
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IJMP,IJA,IJB,IJE,EALU,I0,E0,I1,E1,I2,E2,I3,E3,IF,EF,
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EDTB,iwr,IPC,IMPC,IMAR,IIR,IMARB;
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wire [7:0] signals;
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assign HALT=ctrl_signal[0];
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wire [7:0] ram_MAR;
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wire IJ;
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//always @(posedge rst or posedge ctrl_signal[0]) begin
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// if(ctrl_signal[0]) HALT=1;
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// else if(rst) HALT=0;
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// else HALT=0;
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//end
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ALU u0(
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.clk(clk),
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.rst(rst),
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.Tgt1(Tgt1),
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.Tgt2(Tgt2),
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.DR0(R0),
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.DR1(R1),
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.DR2(R2),
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.DR3(R3),
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.IADD(IADD),
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.ISUB(ISUB),
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.IADC(IADC),
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.ISBB(ISBB),
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.IMUL(IMUL),
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.IDIV(IDIV),
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.IINC(IINC),
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.IDEC(IDEC),
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.ISHL(ISHL),
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.ISHR(ISHR),
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.INOT(INOT),
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.INEG(INEG),
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.IAND(IAND),
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.IOR(IOR),
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.IJMP(IJMP),
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.IJA(IJA),
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.IJB(IJB),
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.IJE(IJE),
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.EALU(EALU),
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.Flags_in(Flag_ALU),
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.Flags_out(ALU_Flag),
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.Dout(ALU_bus),
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.Dout_R1(ALU_Low8),
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.IJ(IJ)
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);
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RA u1(
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.clk(clk),
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.rst(rst),
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.I0(I0),
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.E0(E0),
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.I1(I1),
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.E1(E1),
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.I2(I2),
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.E2(E2),
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.I3(I3),
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.E3(E3),
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.IF(IF),
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.EF(EF),
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.IMUL(IMUL),
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.IDIV(IDIV),
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.Din(bus_R),
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.DinA(ALU_Low8),
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.Flags_in(ALU_Flag),
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.Dout0(R_bus),
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.Flags_out(Flag_ALU),
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.DR0(R0),
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.DR1(R1),
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.DR2(R2),
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.DR3(R3)
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);
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//DR u2(
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// .clk(clk),
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// .IDFR(IDFR),
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// .IDFB(IDFB),
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// .EDTB(EDTB),
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// .Din_RAM(ram_DR),
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// .Din_BUS(bus_DR),
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// .rst(rst),
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// .Dout_RAM(DR_ram),
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// .Dout_BUS(DR_bus)
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//);
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MAR u3(
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.clk(clk),
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.IMAR(IMAR),
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.IMARB(IMARB),
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.Din(PC_MAR),
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.Din_BUS(ram_MAR),
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.rst(rst),
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.Dout(MAR_ram)
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);
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ram_ip u4(
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.clk(clk),
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.iwr(iwr),
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.EDTB(EDTB),
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.addr(MAR_ram),
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.din(bus_DR),
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.dout(DR_bus),
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.to_MAR(ram_MAR)
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);
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PC u5(
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.clk(clk),
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.IPC(IPC),
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.IMPC(IMPC),
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.IJ(IJ),
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.rst(rst),
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.Din(bus_PC),
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.Dout(PC_MAR)
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);
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dbus u6(
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.DR_bus(DR_bus),
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.R_bus(R_bus),
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.ALU_bus(ALU_bus),
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.bus_A(bus_A),
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.bus_B(bus_B),
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.bus_IR(bus_IR),
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.bus_PC(bus_PC),
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.bus_MAR(bus_MAR),
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.bus_R(bus_R),
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.bus_DR(bus_DR)
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);
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IR u7(
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.clk(clk),
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.rst(rst),
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.IIR(IIR),
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.Din(bus_IR),
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.Dout(IR_Decoder)
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);
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Decoder u8(
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.cmd(IR_Decoder),
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.res(ctrl_signal),//26 updatig
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.Tgt1(Tgt1),
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.Tgt2(Tgt2)
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);
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SG u9(
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.clk(clk),
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.rst(rst),
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.signals(signals));
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Controller u10(
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ctrl_signal,
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Tgt1,
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Tgt2,
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signals,
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IA,IB,IADD,ISUB,IADC,ISBB,IMUL,IDIV,
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IINC,IDEC,ISHL,ISHR,INOT,INEG,IAND,IOR,
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IJMP,IJA,IJB,IJE,EALU,I0,E0,I1,E1,I2,E2,I3,E3,IF,EF,
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IDFR,IDFB,EDTB,iwr,IPC,IMPC,IMAR,IIR,IMARB
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);
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endmodule
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