29 lines
520 B
Verilog
29 lines
520 B
Verilog
`timescale 1ns / 1ps
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module ram_ip(
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input wire clk,iwr,EDTB,
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input wire [5:0] addr,
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input wire [7:0] din,
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output wire [7:0] dout,
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output wire [7:0] to_MAR
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);
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wire [7:0] ram_data;
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assign to_MAR=ram_data;
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blk_mem_gen_0 ram (
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.clka(~clk), // input wire clka
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.wea(iwr), // input wire [0 : 0] wea
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.addra(addr), // input wire [5 : 0] addra
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.dina(din), // input wire [7 : 0] dina
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.douta(ram_data) // output wire [7 : 0] douta
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);
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Tri T(
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.din(ram_data),
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.en(EDTB),
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.dout(dout)
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);
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endmodule
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