38 lines
1.1 KiB
Verilog
38 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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module Controller_tb;
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reg clk,rst;
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reg [27:0] ctrl;
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reg [3:0] Tgt1,Tgt2;
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wire [7:0] T;
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wire IA,IB,IADD,ISUB,IADC,ISBB,IMUL,IDIV,
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IINC,IDEC,ISHL,ISHR,INOT,INEG,IAND,IOR,
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IJMP,IJA,IJB,IJE,EALU,I0,E0,I1,E1,I2,E2,I3,E3,IF,EF,
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IDFR,IDFB,EDTB,iwr,IPC,IMPC,IMAR,IIR,IMARB;
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Controller u0(ctrl,
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Tgt1,Tgt2,
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T,
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IA,IB,IADD,ISUB,IADC,ISBB,IMUL,IDIV,
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IINC,IDEC,ISHL,ISHR,INOT,INEG,IAND,IOR,
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IJMP,IJA,IJB,IJE,EALU,I0,E0,I1,E1,I2,E2,I3,E3,IF,EF,
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IDFR,IDFB,EDTB,iwr,IPC,IMPC,IMAR,IIR,IMARB) ;
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SG u1(clk,rst,T);
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initial begin
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clk = 1'b1;
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rst=1;
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end
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always #5 clk = ~clk;
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initial begin
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#80 ctrl=28'b0000_0000_0000_1000_0000_0000_0000;Tgt1=4'b0001;Tgt2=4'b1000;
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#80 ctrl=28'b0000_0000_0000_0000_0010_0000_0000;Tgt1=4'b0001;Tgt2=4'b0000;
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#80 ctrl=28'b0010_0000_0000_0000_0000_0000_0000;Tgt1=4'b0001;Tgt2=4'b0000;
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#80 ctrl=28'b0000_0000_0000_0001_0000_0000_0000;Tgt1=4'b0001;Tgt2=4'b0000;
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#80 ctrl=28'b0000_0000_0000_0000_0000_0000_0001;Tgt1=4'b0000;Tgt2=4'b0000;
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end
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endmodule
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