42 lines
679 B
Verilog
42 lines
679 B
Verilog
`timescale 1ns / 1ps
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module Decoder_tb;
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reg [7:0] cmd;
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wire [27:0] res;
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wire [3:0] Tgt1, Tgt2;
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Decoder dut(cmd,res,Tgt1,Tgt2);
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initial begin
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#10 cmd=8'b00000000;
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#10 cmd=8'b00000001;
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#10 cmd=8'b00000010;
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#10 cmd=8'b11000000;
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#10 cmd=8'b11000101;
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#10 cmd=8'b11001010;
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#10 cmd=8'b11001111;
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#10 cmd=8'b11010000;
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#10 cmd=8'b11010101;
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#10 cmd=8'b11011010;
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#10 cmd=8'b11011111;
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#10 cmd=8'b11100000;
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#10 cmd=8'b11100101;
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#10 cmd=8'b11101010;
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#10 cmd=8'b00011100;
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#10 cmd=8'b00100011;
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#10 cmd=8'b00111011;
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#10 cmd=8'b01000100;
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#10 cmd=8'b01010100;
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#10 cmd=8'b01101010;
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#10 cmd=8'b01110011;
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#10 cmd=8'b10001010;
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#10 cmd=8'b10011111;
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#10 cmd=8'b10100000;
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#10 $stop;
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end
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endmodule
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