43 lines
549 B
Verilog
43 lines
549 B
Verilog
`timescale 1ns / 1ps
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module PC_tb(
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);
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reg clk,IPC, IMPC, rst,IJ;
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reg [7:0] Din;
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wire [5:0] Dout;
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PC u0(
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.clk(clk),
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.IPC(IPC),
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.IMPC(IMPC),
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.IJ(IJ),
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.rst(rst),
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.Din(Din),
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.Dout(Dout)
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);
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initial begin
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clk = 1'b1;
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rst=0;
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end
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always #5 clk=~clk;
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initial begin
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#10 rst=1;
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#10 IPC=1;
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#10 IPC=1;
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#10 IPC=1;
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#10 IMPC=1; Din=6'h11;
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#10 IMPC=1;IJ=1;IPC=0;Din=6'h15;
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#10 IPC=1;IMPC=0;IJ=0;
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#10 IMPC=1;IJ=1;IPC=0; Din=6'h20;
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#10 IPC=1;IMPC=0;IJ=0;
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#10 IPC=1;IMPC=0;
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#10 $stop;
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end
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endmodule
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