62 lines
1.6 KiB
Verilog
62 lines
1.6 KiB
Verilog
`timescale 1ns / 1ps
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module RA_tb(
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);
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reg clk,rst,I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL,IDIV;
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reg [7:0] Din,Din_Low, Flags_in;
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wire [7:0] Dout0, Flags_out;
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wire [7:0] DR0, DR1, DR2, DR3;
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RA u0(
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.clk(clk),
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.rst(rst),
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.I0(I0),
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.E0(E0),
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.I1(I1),
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.E1(E1),
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.I2(I2),
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.E2(E2),
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.I3(I3),
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.E3(E3),
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.IF(IF),
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.EF(EF),
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.IMUL(IMUL),
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.IDIV(IDIV),
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.Din(Din),
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.DinA(Din_Low),
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.Flags_in(Flags_in),
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.Dout0(Dout0),
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.Flags_out(Flags_out),
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.DR0(DR0),
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.DR1(DR1),
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.DR2(DR2),
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.DR3(DR3)
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);
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initial begin
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clk = 1'b1;
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rst=1;
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{I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0000_000;IDIV=0;
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end
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always #5 clk = ~clk;
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initial begin
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#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b1000_0000_000;Din = 8'd12;IDIV=0;
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#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0100_0000_000;Din = 8'd13;
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#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0010_0000_000;Din = 8'd14;
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#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0001_0000_000;Din = 8'd15;
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#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_1000_000;
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#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0100_000;
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#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0010_000;
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#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0001_000;
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#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0000_001;Din_Low = 8'd21;
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#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0100_000;Din = 8'd20;
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#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0000_100;Flags_in = 8'd23;
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#10 {I0,I1,I2,I3,E0,E1,E2,E3,IF,EF,IMUL}=11'b0000_0000_010;
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#10 $stop;
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end
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endmodule
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