25 lines
323 B
Verilog
25 lines
323 B
Verilog
`timescale 1ns / 1ps
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module Tri_tb(
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);
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reg [7:0] din;
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reg en;
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wire [7:0] dout;
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Tri u0(din,en,dout);
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initial begin
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#10 din=8'd11; en=1;
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#10 din=8'd12; en=1;
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#10 din=8'd13; en=0;
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#10 din=8'd14; en=0;
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#10 din=8'd15; en=0;
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#10 din=8'd16; en=1;
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#10 din=8'd17; en=1;
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#10 din=8'd18; en=1;
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#5 $stop;
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end
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endmodule
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