29 lines
319 B
Verilog
29 lines
319 B
Verilog
`timescale 1ns / 1ps
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module cpu_tb;
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reg clk,rst;
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wire [7:0] bus,ram;
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wire [5:0] MAR;
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wire [27:0] ctrl_signal;
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wire [7:0] R0,R1,R2,R3;
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wire HALT;
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cpu DUT(clk,rst,
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bus,ram,
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MAR, ctrl_signal,
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R0,R1,R2,R3,HALT);
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initial begin
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#5 rst=0;clk=1;
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#10 rst=1;
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#10 rst=0;
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#55
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#10 rst=1;
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end
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always #5 clk=~clk;
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endmodule
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