47 lines
916 B
Verilog
47 lines
916 B
Verilog
`timescale 1ns/10ps
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module ram_ip_tb();
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reg we,clk,EDTB;
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reg [5:0] addr;
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reg [7:0] data_in;
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wire [7:0] data_out;
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wire [7:0] DR_MAR;
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ram_ip DUT(
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.iwr (we),
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.clk (clk),
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.EDTB(EDTB),
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.addr (addr),
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.din (data_in),
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.dout (data_out),
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.to_MAR(DR_MAR)
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);
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initial begin
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#20 we = 1'b0;EDTB=1;clk = 1'b0;addr = 6'd0;
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end
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always #10 clk = ~ clk;
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initial begin
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#20 we = 1'b0;
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#20 addr = 6'd0;
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#20 addr = 6'd1;
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#20 addr = 6'd2;
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#20 addr = 6'd3;
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#20 addr = 6'd4;
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#20 addr = 6'd5;
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#20 we = 1'b1; addr = 6'd0; data_in = 8'h3e;
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#20 addr = 6'd1; data_in = 8'h6;
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#20 addr = 6'd2; data_in = 8'hc6;
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#20 addr = 6'd3; data_in = 8'h7;
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#20 addr = 6'd4; data_in = 8'h76;
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#20 addr = 6'd5; data_in = 8'b0000_0000;
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#20 addr = 6'd6; data_in = 8'bxxxx_xxxx;
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#20 we = 1'b0;
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#20 addr = 6'd6;
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#20 addr = 6'd5;
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#20 addr = 6'd4;
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#20 addr = 6'd3;
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#20 addr = 6'd2;
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#20 addr = 6'd1;
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#20 $stop;
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end
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endmodule
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