19 lines
262 B
Verilog
19 lines
262 B
Verilog
`timescale 1ns / 1ps
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module IR(
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input wire clk,
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input wire rst,
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input wire IIR,
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input wire [7:0] Din,
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output wire [7:0] Dout
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);
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LS377 u_IR(
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.clk(clk),
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.rst(rst),
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.EN(IIR),
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.D(Din),
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.Q(Dout)
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);
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endmodule
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