24 lines
534 B
Verilog
24 lines
534 B
Verilog
`timescale 1ns / 1ps
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module MAR(
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input wire clk,
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input wire IMAR,
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input wire IMARB,
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input wire [5:0] Din,//PC计数器传来的地址
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input wire [7:0] Din_BUS,//PC计数器传来的地址
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input wire rst,
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output wire [5:0] Dout
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);
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reg [5:0] addr=6'b000000;
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assign Dout=addr;
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always @ (posedge IMAR or posedge IMARB or negedge rst) begin
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if(rst==0) addr=6'b000000;
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else if(IMAR==1) addr = Din;
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else if(IMARB==1) addr = Din_BUS[5:0];
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else addr=addr;
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end
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endmodule
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