19 lines
497 B
Verilog
19 lines
497 B
Verilog
`timescale 1ns / 1ps
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module MUX(
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input [7:0] D1,D2,
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input ctrl,
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output wire [7:0] D
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);
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assign D[7] = (D1[7]&&~ctrl)|| (D2[7]&&ctrl);
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assign D[6] = (D1[6]&&~ctrl)|| (D2[6]&&ctrl);
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assign D[5] = (D1[5]&&~ctrl)|| (D2[5]&&ctrl);
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assign D[4] = (D1[4]&&~ctrl)|| (D2[4]&&ctrl);
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assign D[3] = (D1[3]&&~ctrl)|| (D2[3]&&ctrl);
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assign D[2] = (D1[2]&&~ctrl)|| (D2[2]&&ctrl);
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assign D[1] = (D1[1]&&~ctrl)|| (D2[1]&&ctrl);
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assign D[0] = (D1[0]&&~ctrl)|| (D2[0]&&ctrl);
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endmodule
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