91 lines
1.5 KiB
Verilog
91 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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module RA(
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input wire clk,//clock
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input wire rst,//1->0 negedge clear
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input wire I0,
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input wire E0,//R0 signal
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input wire I1,
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input wire E1,//R1 signal
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input wire I2,
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input wire E2,//R2 signal
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input wire I3,
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input wire E3,//R3 signal
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input wire IF,
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input wire EF,//Flags
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input wire IMUL,//ctrl signal MUL AUL to R1
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input wire IDIV,
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input wire [7:0] Din,//R0~R3
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input wire [7:0] DinA,//low 8 bit from ALU to R1
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input wire [7:0] Flags_in,//Flags in
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output wire [7:0] Dout0,
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// output wire [7:0] Dout1,
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//output wire [7:0] Dout2,
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//output wire [7:0] Dout3,//R out
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output wire [7:0] Flags_out,//Flags out
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output wire [7:0] DR0,
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output wire [7:0] DR1,
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output wire [7:0] DR2,
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output wire [7:0] DR3
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);
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wire [7:0] Dto_R1;
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R r0(
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.clk(clk),
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.rst(rst),
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.IR(I0),
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.ER(E0),
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.Din(Din),
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.Dout(Dout0),
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.Dshow(DR0)
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);
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MUX mux(
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.D1(Din),
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.D2(DinA),
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.ctrl(IMUL||IDIV),
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.D(Dto_R1)
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);
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R r1(
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.clk(clk),
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.rst(rst),
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.IR(IMUL||IDIV||I1),
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.ER(E1),
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.Din(Dto_R1),
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.Dout(Dout0),
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.Dshow(DR1)
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);
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R r2(
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.clk(clk),
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.rst(rst),
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.IR(I2),
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.ER(E2),
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.Din(Din),
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.Dout(Dout0),
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.Dshow(DR2)
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);
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R r3(
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.clk(clk),
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.rst(rst),
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.IR(I3),
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.ER(E3),
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.Din(Din),
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.Dout(Dout0),
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.Dshow(DR3)
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);
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R psw(
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.clk(clk),
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.rst(rst),
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.IR(IF),
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.ER(EF),
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.Din(Flags_in),
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.Dout(Flags_out)
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);
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endmodule
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