26 lines
569 B
Verilog
26 lines
569 B
Verilog
`timescale 1ns / 1ps
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//½ÚÅÄ·¢ÉúÆ÷ clk rst0
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module SG(
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input wire clk,
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input wire rst,
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output wire [7:0] signals
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);
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reg [7:0] state = 8'b10000000;
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assign signals = state;
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always @(posedge clk or negedge rst) begin
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if(rst == 0)
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state = 8'b10000000;
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else if(clk==1) begin
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state[7:1] <= state[6:0];
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state[0] <= state[7];
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end
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end
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//wire [7:0] original;
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//assign original = {~rst,rst,rst,rst,rst,rst,rst,rst};
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//assign signals[7:0] = (rst&{signals[6:0],signals[7]})|(~rst&original[7:0]) ;
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endmodule
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