19 lines
380 B
Verilog
19 lines
380 B
Verilog
`timescale 1ns / 1ps
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module dbus(
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input [7:0] DR_bus,R_bus,ALU_bus,
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output wire [7:0] bus_A,bus_B,bus_IR,bus_PC,bus_R,bus_DR,bus_MAR
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);
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wire [7:0] data;
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assign data = DR_bus;
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assign data = R_bus;
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assign data = ALU_bus;
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assign bus_A=data;
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assign bus_B=data;
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assign bus_IR=data;
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assign bus_PC=data;
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assign bus_R=data;
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assign bus_DR=data;
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assign bus_MAR=data;
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endmodule
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