24 lines
422 B
Verilog
24 lines
422 B
Verilog
`timescale 1ns / 1ps
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//clk EN1 rst0 D -> Q
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module LS377(
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input wire clk,
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input wire EN,
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input wire rst,
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input wire [7:0] D,
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output wire [7:0] Q,
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output wire [7:0] Dshow
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);
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reg [7:0] data=8'b0000_0000;
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assign Q = data;
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assign Dshow=data;
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always @ (posedge clk or negedge rst) begin
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if(rst == 0)
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data = 8'b0000_0000;
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else if(EN == 1)
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data = D;
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end
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endmodule
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